AT89LP51ED2-20AU Atmel, AT89LP51ED2-20AU Datasheet - Page 37

• Manufacturer Part Number: AT89LP51ED2-20AU
• Description: 8-bit Microcontrollers - MCU 64KB 20MHz 2.4V-5.5V
• Manufacturer: Atmel

Specifications of AT89LP51ED2-20AU

• Rohs: yes
• Core: 8051
• Processor Series: AT89x
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 256 B
• On-chip Adc: Yes
• Operating Supply Voltage: 2.4 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-44
• Mounting Style: SMD/SMT
• Data Rom Size: 4 KB
• Interface Type: 2-Wire, SPI, UART
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Program Memory Type: Flash
• Factory Pack Quantity: 160

5.4
3714A–MICRO–7/11
Enhanced Dual Data Pointers
The AT89LP51RD2/ED2/ID2 provides two 16-bit data pointers: DPTR0 and DPTR1. The data
pointers are used by several instructions to access the program or data memories. The
Auxiliary 1 Register (AUXR1) and Data Pointer Configuration Register (DPCF) control operation
of the dual data pointers (see
AUXR1 selects which data pointer is currently referenced by instructions including the DPTR
operand. Each data pointer may also be accessed at a pair of SFR addresses that also depend
on the DPS value. The data pointer referenced by DPS is located at the register pair DPL and
DPH (82H an 83H), and the alternate data pointer not referenced by DPS is located at the regis-
ter pair DPLB and DPHB (D4H and D5H). When DPS is toggled, the two data pointers also swap
which SFR pair will access them as shown in
two methods for fast context switching of the data pointers:
Table 5-2.
SFR
DPL (82H)
DPH (83H)
DPLB (D4H)
DPHB (D5H)
• Bit 2 of AUXR1 is hard-wired as a logic 0. The DPS bit may be toggled (to switch data
• In some cases, both data pointers must be used simultaneously. To prevent frequent toggling
pointers) simply by incrementing the AUXR1 register, without altering other bits in the register
unintentionally. This is the preferred method when only a single data pointer will be used at
one time.
of DPS, the AT89LP51RD2/ED2/ID2 supports a prefix notation for selecting the opposite data
pointer per instruction. All DPTR instructions, with the exception of JMP @A+DPTR, when
prefixed with an 0A5H opcode will use the inverse value of DPS (DPS) to select the data
pointer. Some assemblers may support this operation by using the /DPTR operand. For
example, the following code performs a block copy within EDATA:
EX:
COPY: MOVX A, @DPTR
For assemblers that do not support this notation, the 0A5H prefix must be declared in-line:
EX:
INC
MOV
MOV
MOV
MOV
INC
MOVX @/DPTR, A
INC
DJNZ R7, COPY
DB
INC
Data Pointer Register Access
AUXR1 ; Toggle DPS
AUXR1, #00H
DPTR, #SRC
/DPTR, #DST
R7, #BLKSIZE
DPTR
/DPTR
0A5H
DPTR
AT89LP51RD2/ED2/ID2 Preliminary
Table 5-6 on page 39
; DPS = 0
; load source address to dptr0
; load destination address to dptr1
; number of bytes to copy
; read source (dptr0)
; next src (dptr0+1)
; write destination (dptr1)
; next dst (dptr1+1)
; equivalent to INC /DPTR
Table
DPS = 0
DP0L
DP0H
DP1L
DP1H
and
5-2. The AT89LP51RD2/ED2/ID2 provides
Table 5-7 on page
DPS = 1
DP1L
DP1H
DP0L
DP0H
39). The DPS bit in
37