ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 9

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
ADCLRCLK
ADCBCLK
DACLRCLK
1.2.
The ACS422x68 provides multiple outputs for analog sound. Audio outputs include:
•
•
Each endpoint features independent volume controls, including a soft-mute capability which can slowly ramp up or
down the volume changes to avoid unwanted audio artifacts.
The ACS422x68 output signal paths consist of digital filters, DACs and output drivers. The digital filters and DACs are
enabled when the ACS422x68 is in ‘playback only’ or ‘record and playback’ mode. The output drivers can be sepa-
rately enabled by individual control bits.
The digital filter and audio processing block processes the data to provide volume control and numerous sound
enhancement algorithms. Two high performance sigma-delta audio DACs convert the digital data into analog.
The digital audio data is converted to oversampled bit streams using 24-bit digital interpolation filters, which then enters
sigma-delta DACs, and become converted to high quality analog audio signals.
DACBCLK
I2C_SDA
ADCOUT
I2C_SCL
HP_DET
DACIN
TEST
MCLK
A 1W/channel (8) or 2W/channel (4) filterless DDX
the speakers typically found in portable equipment, providing high fidelity, high efficiency, and excellent sound
quality.
A line-out/capless stereo headphone port with ground referenced outputs, capable of driving headphones
without requiring an external DC blocking capacitor.
Audio Outputs
Clocking
Control
PLL
Processing
Processing
Audio
Audio
Bass/Treble Enhancement
Dynamic Range Expander
Audio Processing
Compressor-limiter
SPEAKER EQ
SYSTEM EQ
3-D effect
VDD_PLL2
Internal Audio Clock(s)
mute
mute
VDD_PLL3
-97 to +30 dB
In 0.5 dB steps
-97 to +30 dB
In 0.5 dB steps
VOL
VOL
DAC Right
DAC Left
VDD_PLL1
Figure 2. ACS422x68 HLA Block Diagram
VSS_PLL VSS_XTAL
ADCR
ADCL
Automatic Level Control
DVDD_CORE
DVDD_IO
-17 to +30dB in 0.75dB steps
-17 to +30dB in 0.75dB steps
D2S
AGC
AGC
9
CPVDD
TM
DVSS
Charge-Pump
+0/+10/+20/+30 dB
+0/+10/+20/+30 dB
D2S
CAP+
Class D amplifier. This amplifier is capable of driving
+
-
Boost
Boost
AVSS
CAP-
DAC Right
DAC Left
2
3
V-
2
CPGND
RIN1
RIN2
LIN1
LIN2
AVDD
3
PVSS
S
PVDD
4
4
Volume
Volume
Digital
Digital
RIN1
RIN2
RIN3
LIN1
LIN2
LIN3
D2S
D2S
vol
vol
DAC
DAC
AGND
Digital PWM
Digital PWM
controller
controller
Vref
Anti-
Anti-
pop
pop
+
-
*Digital Microphone Products
BTL
BTL
HP
HP
MIC Bias
LIN1
LIN2
LIN3/DMIC_CLK*
RIN1
RIN2
RIN3/DMIC_DAT*
Vref
AFILT1
AFILT2
HP Out Left
HP Out Right
Class D Left+
Class D Left-
Class D Right+
Class D Right-
ACS422X68
V1.6 01/13