ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 57

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
R14 (0Eh)
ALC Control 0
R15 (0Fh)
ALC Control 1
R16 (10h)
ALC Control 2
R17 (11h)
ALC Control 3
Register Address
4.7.2.
ALC Registers
Bit
7:3
1:0
6:4
3:0
6:4
3:0
7:4
3:0
2
7
7
ALC MODE
MAXGAIN
MINGAIN
ALCSEL
RSVD
RSVD
RSVD
Label
ALCL
HLD
DCY
[1:0]
[2:0]
[3:0]
[3:0]
[3:0]
ATK
[3:0]
Table 64. ALC Control Registers
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
(+30dB)
(192ms)
Default
(-12dB)
(24ms)
00000
57
(OFF)
(0ms)
0000
0010
1011
0011
000
111
00
0
0
0
Reserved
0: ALC Mode
ALC function select
00 = ALC off (PGA gain set by register)
01 = Right channel only
10 = Left channel only
11 = Stereo (PGA registers unused)
Note: ensure that LINVOL and RINVOL settings (reg.
0 and 1) are the same before entering this mode.
Reserved
Set Maximum Gain of PGA
111: +30dB
110: +24dB
….(-6dB steps)
001: -6dB
000: -12dB
ALC target – sets signal level at ADC input
0000 = -28.5dB fs
0001 = -27.0dB fs
… (1.5dB steps)
1110 = -7.5dB fs
1111 = -6dB fs
Sets the minimum gain of the PGA
000 = -17.25db
001 = -11.25
...
110 = +18.75dB
111 = +24.75db
where each value represents a 6dB step.
ALC hold time before gain is increased.
0000 = 0ms
0001 = 2.67ms
0010 = 5.33ms
… (time doubles with every step)
1111 = 43.691s
ALC decay (gain ramp-up) time
0000 = 24ms
0001 = 48ms
0010 = 96ms
… (time doubles with every step)
1010 or higher = 24.58s
ALC attack (gain ramp-down) time
0000 = 6ms
0001 = 12ms
0010 = 24ms
… (time doubles with every step)
1010 or higher = 6.14s
1: Limiter mode
Description
ACS422X68
V1.6 01/13