ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet
ACS422A68TAGZBX8
Specifications of ACS422A68TAGZBX8
Related parts for ACS422A68TAGZBX8
ACS422A68TAGZBX8 Summary of contents
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PORTABLE CONSUMER CODEC LOW-POWER, HIGH-FIDELITY INTEGRATED CODEC The ACS422x68 is a low-power, high-fidelity integrated CODEC targeted at portable applications such as tablet computers, personal navigation devices, portable projec- tors and speaker docks. In addition to a high-fidelity low-power CODEC, the ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC TABLE OF CONTENTS 1. OVERVIEW ................................................................................................................................ 8 1.1. Block Diagrams ..................................................................................................................................8 1.2. Audio Outputs ....................................................................................................................................9 1.3. Audio Inputs .....................................................................................................................................10 2. POWER MANAGEMENT ........................................................................................................ 11 2.1. Control Registers .............................................................................................................................11 2.2. Stopping the Master Clock ...............................................................................................................12 3. ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.5.1. ADC Signal Path Control Register .....................................................................................54 4.5.2. ADC High Pass Filter Enable modes .................................................................................54 4.6. Digital ADC Volume Control .............................................................................................................54 4.6.1. ADC Digital Registers ........................................................................................................55 4.7. Automatic Level Control (ALC) ........................................................................................................55 4.7.1. ALC Operation ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 9.4.5. ACS422x68NAG Data and Control Pins ............................................................................88 9.4.6. ACS422x68NAG Clock Pins ..............................................................................................89 10. PACKAGE INFORMATION ................................................................................................... 90 10.1. TAG/TLA Package Drawing ...........................................................................................................90 10.2. Pb Free Process- Package Classification Reflow Temperatures ..................................................90 11. NAG/HLA PACKAGE INFORMATION ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC LIST OF FIGURES Figure 1. ACS32201 TLA Block Diagram .........................................................................................................8 Figure 2. ACS32201 HLA Block Diagram ........................................................................................................9 Figure 3. Output Audio Processing ................................................................................................................13 Figure 4. Prescaler & EQ Filters ....................................................................................................................16 Figure 5. 6-Tap IIR Equalizer ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC LIST OF TABLES Table 1. Power Management Register 1 ........................................................................................................11 Table 2. Power Management Register 2 ........................................................................................................11 Table 3. Power Management Register1 -- Master Clock Disable ..................................................................12 Table 4. DC_COEF_SEL Register .................................................................................................................13 Table 6. Volume ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Table 59. Power Management 1 Register - Mic Bias Enable .........................................................................51 Table 60. INVOL L&R Registers ....................................................................................................................52 Table 61. CNVRTR0 Register ........................................................................................................................54 Table 62. ADC HPF Enable ...........................................................................................................................54 Table 63. L/R ADC Digital Volume Registers ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 1. OVERVIEW 1.1. Block Diagrams The ACS422x68 is an advanced low power codec with integrated amplifiers and timing generators. To support the design of audio subsystems in a portable device, the ACS422x68 features an intelligent ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Clocking VDD_PLL2 PLL Internal Audio Clock(s) MCLK I2C_SDA I2C_SCL Control HP_DET TEST Audio Processing Bass/Treble Enhancement SYSTEM EQ DACBCLK SPEAKER EQ DACLRCLK 3-D effect Compressor-limiter DACIN Dynamic Range Expander ADCOUT ADCLRCLK ADCBCLK Audio mute Processing ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC To enhance the sound available from the small, low-power speakers typically found in a portable device, the ACS422x68 provides numerous audio enhancement capabilities. The ACS422x68 features dual, independent, pro- grammable left/right 6-band equalization, allowing the ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 2. POWER MANAGEMENT 2.1. Control Registers The ACS422x68 has control registers to enable system software to control which functions are active. To minimize power consumption, unused functions should be disabled. To avoid audio artifacts, it ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 2.2. Stopping the Master Clock In order to minimize digital core power consumption, the master clock may be stopped in Standby and OFF modes by setting the DIGENB bit (R25, bit 0). Register Address Bit ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3. OUTPUT AUDIO PROCESSING DACCRAM 00h – 3Dh PA DACCRAM 40h – 7Dh Treble DACCRAM ADh DACCRAM 97h – ADh Mono DC PA Mix Removal Bass DACCRAM AEh – AFh DACCRAM 96h DACCRAM AFh 18h ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Register Address Bit 7:6 5:4 R31 (1Fh) 3:2 CONFIG0 1 0 3.2. Volume Control The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps). The level ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Register Address Bit 7 6 5:4 R33 (21h) 3 Gain Control (GAINCTL 3.3. Digital DAC Volume Control The signal volume can be controlled digitally, across a gain and attenuation range of ...
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... EQ filters in case the EQ filters introduce gain, and would thus clip if not prescaled. IDT provides a tool to enable an audio designer to determine appropriate coefficients for the equal- izer filters. The filters enable the implementation of a 6-band parametric equalizer with selectable fre- quency bands, gain, and filter characteristics (high, low, or bandpass) ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.4.2. EQ Registers • EQ Filter Enable Register Register Address Bit 7 6:4 R32 (20h) CONFIG1 3 2:0 • DACCRAM Read Data (0x3D–LO, 0x3E–MID, 0x3F–HI), DACCRAM Write Data (0x3A–LO, 0x3B–MID, 0x3C–HI) Registers These two 24-bit ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • DACCRAM Address Register This 7-bit register provides the address to the internal RAM when doing indirect writes/reads to the DAC Coefficient RAM. Register Address Bit R64 (40h) 7:0 DACCRADDR • DACCRAM STATUS Register This ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Reading back a value from the DACCRAM is done in this manner: 1. Write target address to DACCRAM_ADDR register.(EQ data is pre-fetched for read even if we don’t use it) 2. Start (or repeat start) ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC EQ 0 Channel 0 Addr Coefficients 0x03 EQ_COEF_0F0_A1 0x04 EQ_COEF_0F0_A2 0x05 EQ_COEF_0F1_B0 0x06 EQ_COEF_0F1_B1 0x07 EQ_COEF_0F1_B2 0x08 EQ_COEF_0F1_A1 0x09 EQ_COEF_0F1_A2 0x0A EQ_COEF_0F2_B0 0x0B EQ_COEF_0F2_B1 0x0C EQ_COEF_0F2_B2 0x0D EQ_COEF_0F2_A1 0x0E EQ_COEF_0F2_A2 0x0F EQ_COEF_0F3_B0 0x10 EQ_COEF_0F3_B1 0x11 ...
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... The gain for a given channel is controlled by the DACVOL registers. The range of gain supported is from -95.625db to 0db in 0.375db steps. If the result of the gain multiply step would result in overflow of the 24-bit output word width, the output is saturated at the max positive or negative value. In addition to simple gain control, the ACS422x68 also provides sophisticated dynamic range control. The dynamic © ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC range control processing element implements limiting, dynamic range compression, and dynamic range expansion functions. 3.6. Limiter The Limiter function will limit the output of the DSP module to the Class-D and DAC modules. If the ...
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... In addition to limiting the bandwidth of the compressed audio common for compressed audio to also compress the dynamic range of the audio. The expansion function in the ACS422x68 can help restore the original dynamics to the audio ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.7.2. Controlling parameters In order to control this processing, there are a number of configurable parameters. The parameters and their ranges are: • Compressor/limiter • Threshold – -40db to 0db relative to full scale. • ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC thresholds. The compressor recalculates the target gain value every block, typically every 10ms. • The gain calculation operates in 3 regions: • • • • Compression region gain calculation: In the compression region, the gain ...
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... Label Type Default RSVD R 0h Reserved CLE Level Detection Mode Lvl_Mode Average 1 = Peak Window width selection for level detection equivalent of 512 samples of selected Base Rate WindowSel RW 0 (~10-16ms equivalent of 64 samples of selected Base Rate (~1.3-2ms) Exp_en enable expander Limit_en ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • Compressor Threshold Register Address Bit R39 (27h) 7:0 COMPTH • Compressor ratio register Register Address Bit 7:5 R40 (28h) CMPRAT 4:0 • Compressor Attack Time Constant Register (Low) Register Address Bit R41 (29h) 7:0 ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • Limiter Target Register Register Address Bit R46 (2Eh) 7:0 LIMTGT • Limiter Attack Time Constant Register (Low) Register Address Bit R47 (2Fh) 7:0 LATKTCL • Limiter Attack Time Constant Register (High) Register Address Bit ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • Expander Attack Time Constant Register (Low) Register Address Bit R53 (35h) 7:0 XATKTCL • Expander Attack Time Constant Register (High) Register Address Bit R54 (36h) 7:0 XATKTCH • Expander Release Time Constant Register (Low) ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 1. If the material common to the two channels is removed, then the speakers will sound more 3- the material for the opposite channel is presented to the current channel inverted, it will ...
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... The enhanced treble function works much like the enhanced bass, however it's intended use is different. The enhanced treble uses a non linear function to add treble harmonics to a signal that has limited high-frequency bandwidth (such as a low bit rate MP3). In this case, the algorithm makes use of the audio fact that presence of audio between 4- good predictor of audio between 10K-20K ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.12. Mute and De-Emphasis The ACS422x68 has a Soft Mute function, which is used to gradually attenuate the digital signal volume to zero. The gain returns to its previous setting if the soft mute is ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.13.2. Interpolation and Filtering AUTO 2X Input Rate = 24 From I2S 57T FIR-A 8/11.024/12kHz (QX): 8kHz 11.025kHz 12kHz 2X Input Rate = 24 From I2S 57T FIR-A 16/22.05/24kHz (HX): 16kHz 22.05kHz 24kHz 2X Input ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.14. Analog Outputs 3.14.1. Headphone Output The HPOut pins can drive a 16 or 32 headphone or alternately drive a line output. The signal vol- ume of the headphone amplifier can be independently adjusted under ...
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... SPKVOLR 6:0 TM 3.14.3. Class D Audio Processing DDX For additional information on the DDX www.idt.com. TM The DDX • Feedback filters are applied to shape any noise. The filters move noise from audible frequencies to frequencies above the audio range. • The PWM block converts the data streams to tri-state PWM signals and sends them to the power stages. • ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The BTL amplifier in ACS422x68 will continuously adjust to power supply changes to ensure that the full scale output power remains constant. This is not an automatic level control. Rather, this function prevents sudden volume ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Constant Output Power error (dB) relative to a target of 8 for an ideal part and the output error if left uncorrected across a 3.1 to 5.5V supply range 3.1 ‐1 ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.14.3.2. Under Voltage Lock Out When the PVDD supply becomes low, the BTL amplifier may be disabled to help prevent undesir- able amplifier operation (overheat) or system level problems (battery under-voltage.) The same circuit that ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • Constant Output Power 3 Register Address Bit 7 R137 (89h) 6 Constant Output Power 3 5:0 • Configuration Register Register Address Bit 7:6 5:4 R31 (1Fh) 3:2 CONFIG0 1 0 • PWM Control 0 ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC • PWM Control 1 Register Register Address Bit 7 6:2 R67 (43h) PWM1 1 0 • PWM Control 2 Register Register Address Bit 7:2 R68 (44h) 1 PWM2 0 pwm_outmode • PWM Control 3 Register ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.15.1. Audio Output Control See Power management section. The output enable bits are also power management bits and the outputs will be turned off when disabled. Register Address Bit R27 (1Bh) 4 ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.15.2.1. Headphone Switch Register Register Address Bit 7 6 5:4 R29 (1Ch) Additional Control 3:2 (CTL 3.15.3. Headphone Operation HPSWEN HPSWPOL ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.16. Thermal Shutdown To avoid overpowering and overheating the codec when the amplifier outputs are driving large currents, the ACS422x68 incorporates a thermal protection circuit. If enabled, and the device temperature reaches approximately 150°C, the ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.16.3. Temperature Limit State Diagram: 3.16.4. Instant Cut Mode This mode can be used to make our algorithm react faster to reduce thermal output but will cause more pronounced volume changes. If enabled: • Only ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.16.5. Short Circuit Protection To avoid damage to the outputs if a short circuit condition should occur, both the headphone and BTL amplifiers imple- ment short circuit protection circuits. The headphone output amplifier will detect ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.16.6.2. Temp Sensor Control/Status Register Register Address Bit 7 6 5:4 R29 (1Dh) Temp Sensor Control/Status (THERMTS) 3:2 1:0 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. Label Type Default Temp sensor high trip point status TripHighStat R ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.16.6.3. Temp Sensor Status Register Register Address Bit 7 6 R30 (1Eh) Speaker Thermal 5:4 Algorithm Control (THERMSPKR1) 3:2 1:0 DecStep[1:0] Register Address Bit 7 ForcePwdStatus R136 (88h) Speaker Thermal Algorithm Status (THERMSPKR2) 6:0 VolStatus[6:0] ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4. INPUT AUDIO PROCESSING 06h ADC Leftt Digital Volume -71. 0.375 dB steps ADC Output Configuration mute VOL mute VOL -71.25 to +24 dB 14h ADC Data Select In 0.375 dB ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.1.1. Input Registers Register Address Bit 7:6 R12 (0Ch) ADC Signal Path Control Left (INSELL) 5:4 3:0 7:6 R13 (0Dh) ADC Signal Path Control Right (INSELR) 5:4 3:0 4.2. Mono Mixing and Output Configuration The ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.2.1. ADC Registers 4.2.1.1. Register Address Bit Label 7:1 R11 (0Bh) ADC Input mode 0 (INMODE) 4.2.1.2. Register Address Bit 7 6 R22 (16h) 5:4 ADC Control (CNVRTR0 4.2.1.3. Register Address ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.3. Microphone Bias The MICBIAS output is used to bias electric type microphones. It provides a low noise reference voltage used for an external resistor biasing network. The MICB control bit is used to enable ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.4.1. Input PGA Software Control Register. Register Address Bit (08h) Left Input Volume (INVOLL) 5 (09h) Right Input Volume (INVOLR) 5:0 R28 (1Ch) Additional Control 0 (CTL) 4.5. ADC ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC AUTO Output Rate = From Analog ADC 8/11.025/12kHz (QX): Output Rate = From Analog ADC 16/22.05/24kHz (HX): Output Rate = From Analog ADC 32/44.1/48kHz (1X): Output Rate = From Analog ADC 64/88.2/96kHz (2X): Full Output ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.5.1. ADC Signal Path Control Register Register Address Bit 7 6 5:4 R22 (16h) ADC Control (CNVRTR0 4.5.2. ADC High Pass Filter Enable modes ADCHPDR ADCHPDL ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.6.1. ADC Digital Registers Register Address Bit R6 (06h) Left ADC 7:0 Digital Volume R7 (07h) Right ADC 7:0 Digital Volume 4.7. Automatic Level Control (ALC) The ACS422x68 has an automatic level control to achieve ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Hold time specifies the delay between detecting a peak level being below target, and the PGA gain beginning to ramp up specified as 2 ramp-down begins immediately if the signal level is above ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.7.2. ALC Registers Register Address Bit 7:3 2 R14 (0Eh) ALC Control 0 1:0 7 6:4 R15 (0Fh) ALC Control 1 3:0 7 6:4 R16 (10h) ALC Control 2 3:0 7:4 R17 (11h) ALC Control ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 4.7.3. Peak Limiter To prevent clipping, the ALC circuit also includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (–1.16dB), the PGA gain is ramped down at the maximum attack ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC SDM Rate DMRate [1: Full Half 10 11 The two DMIC data inputs are shown connected to the ADCs through the same multiplexors as the analog ports. Although the ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC The codec supports the following digital microphone configurations: Digital Mics Data Sample 0 N/A 1 Single Edge 2 Double Edge Digital Microphone Single Microphone not supporting multiplexed output. DMIC_DAT DMIC_CLK Single “Left” Microphone, DMIC input ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Digital Microphones DMIC_DAT DMIC_CLK 4.8.1. DMIC Register Register Address Bit 7 6:5 R36 (24h) 4 D-Mic Control (DMICCTL) 3:2 1:0 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. Off-Chip On-Chip External Multiplexer On-Chip Multiplexer DMIC_DAT Pin DMIC_CLK Pin ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 5. DIGITAL AUDIO AND CONTROL INTERFACES 5.1. Data Interface For digital audio data, the ACS422x68 uses five pins to input and output digital audio data. • ADCDOUT: ADC data output • ADCLRCK: ADC data alignment ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 5.3. Audio Data Formats The ACS422x68 supports 3 common audio interface formats and programmable clocking that provides broad compat- ibility with DSPs, Consumer Audio and Video SOCs, FPGAs, handset chipsets, and many other products. In ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 2 5. Format Audio Interface mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 5.7.2. Audio Interface Output Tri-state TRI is used to tri-state the ADCDOUT, ADCLRCK, DACLRCK, ADCBCLK, and DACBCLK pins. In Slave mode (MAS- TER=0) only ADCDOUT will be tri-stated since the other pins are configured as ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 5.7.4. Bit Clock and LR Clock Mode Selection BLRCM 1 MS MODE [2:0] 0 000 Independent Input for playback path 0 001 Independent Input for playback path Shared BCLK Input for playback and 0 010 ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 3.ADC (record path) is off when ADCL, and ADCR power states are off (PGA, D2S, Boost power states are not considered.) 5.7.5. ADC Output Pin State Tri-state (TRI 5.7.6. Audio Interface Control 3 ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC . Register Address Bit R23/R25 (17h/19h ADC/DAC Sample 7:6 Rate Control Table 74. Master Mode BCLK Frequency Control Register The BCM mode bit clock generator produces 16, 20 bit cycles per sample. LRCLK ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC SCL SDA Device Address DA[6:0] START The ACS422x68 has device address D2. 5.9.2. Multiple Write Cycle The controller may write more than one register within a single write cycle. To write additional regis- ters, the ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC SCL SDA Device Address DA[6:0] START The ACS422x68 has device address D2. 5.9.4. Multiple Read Cycle The controller may read more than one register within a single read cycle. To read additional registers, the controller ...
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... R127 (7Fh) REVID 3:0 Note: Contact IDT for device and revision information. 5.9.5.2. The ACS422x68 registers may be reset to their default values using the reset register. Writing a spe- cial, non-zero value to this register causes all other registers to assume their default states. Device status bits will not necessarily change their values depending on the state of the device. ...
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... The ACS422x68 is designed to use an external clock (MCLK) whose frequency is 11.2896MHz when playing 44.1KHz audio or 12.288MHz when playing 48KHz audio. Other frequencies are acceptable, but please contact your IDT support representative for assistance in ensuring compati- bility. An active MCLK is required when power is applied for proper operation. MCLK is required for I2S communication ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Register Address Bit 7:6 5 R25 (19h) DAC Sample Rate Control 4:3 (DACSR) 2:0 The clocking of the ACS422x68 is controlled using the BR[1:0] and BM[2:0] control bits. Each value of BR[1:0] + BM[2:0]selects one ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC DAC and ADC Sigma-Delta modulators run at a high rate for the best audio quality. The modulator rates for the con- verters may be forced to run at half their nominal rate to conserve power. ...
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... Stresses above the ratings listed below can cause permanent damage to the ACS422x68. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Func- tional operation of the device at these or any other conditions above those indicated in the opera- tional sections of the specifications is not implied ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 7.2. Device Characteristics ( ºC, DVDD_CORE=DVDD_IO=AVDD=1.9V, PVDD=3.6V, 997Hz signal, fs=48KHz, Input Gain=0dB, 24-bit audio ) ambient Parameter Analog Inputs ( IN1 IN2, IN3, IN1 Full Scale Input Voltage V ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC Parameter Total Harmonic Distortion THD+N +Noise Speaker Outputs (L+, L-, R+, R- with 8ohms bridge-tied load) Full Scale Output Level V FSOV Output Power P O Signal to Noise Ratio SNR Total Harmonic Distortion + ...
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... ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 1.Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 2.THD+N ratio as defined in AES17 and outlined in AES6id,non-weighted, swept over kHz bandwidth. ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 8. REGISTER MAP Register Name Remarks (D15:9) R0 (00h) HPVOLL Left HP volume R1 (01h) HPVOLR Right HP volume R2 (02h) SPKVOLL SPKR Left volume R3 (03h) SPKVOLR SPKR Right volume R4 (04h) DACVOLL Left ...
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... R137-R255 Reserved (88h-FFh) 1. Device ID is dependent upon clock programming. 2. For device revision information, please contact IDT. Note: • Registers not described in this map should be considered “reserved”. • Numerous portions of the register map are compatible with popular codecs from other vendors. ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 9. PIN INFORMATION 9.1. ACS422x68TAG Pin Diagram Vref 01 AVSS 02 AVSS 03 AVDD 04 AVDD 05 AFILT2 06 AFILT1 07 RIN3 08 LIN3 09 DVDD_CORE 10 DVSS 11 DVDDIO 12 DACBCLK 13 DACLRCLK 14 ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC ACS422x68TAG Pin Diagram Vref 01 AVSS 02 AVSS 03 AVDD 04 AVDD 05 AFILT2 06 AFILT1 07 DMIC_DAT 08 DMIC_CLK 09 DVDD_CORE 10 DVSS 11 DVDDIO 12 DACBCLK 13 DACLRCLK 14 DACDIN 15 ADCBCLK 16 ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 9.2. ACS422x68NAG Pin Diagram A10 Vref A9 AVSS AVSS A8 AVDD AFILT1 A7 AVDD RIN3 A6 AFILT2 DVSS A5 LIN3 DACBCLK A4 DVDD_CORE DACDIN A3 DVDDIO ADCLRCLK A2 DACLRCLK ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. B10 ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC ACS422x68NAG Pin Diagram A10 B10 Vref A9 AVSS AVSS A8 AVDD AFILT1 A7 AVDD DMIC_DAT A6 AFILT2 DVSS A5 DMIC_CLK DACBCLK A4 DVDD_CORE DACDIN A3 DVDDIO ADCLRCLK A2 DACLRCLK ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. C10 ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 9.3. ACS422x68TAG Pin Tables 9.3.1. ACS422x68TAG Power Pins Pin Name PVDD PVSS DVDD_Core DVDDIO DVSS AVDD AVSS CPVDD CAP+ CAP- V- CPGND VDD_PLL1 VDD_PLL3 VDD_PLL2 VDD_XTAL VSS_PLL VSS_XTAL Total Pins: 30 9.3.2. ACS422x68TAG Reference Pins ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 9.3.3. ACS422x68TAG Analog Input Pins Pin Name LIN1 RIN1 LIN2 RIN2 LIN3 DMIC_CLK RIN3 DMIC_DAT Total Pins: 6 9.3.4. ACS422x68TAG Analog Output Pins Pin Name HP_L HP_R Class D L+ Class D L- Class D ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 9.3.6. ACS422x68TAG Clock Pins Pin Name MCLK NC Total Pins: 12 9.4. ACS422x68NAG Pin Tables 9.4.1. ACS422x68NAG Power Pins Pin Name PVDD PVSS DVDD_Core DVDDIO DVSS AVDD AVSS CPVDD CAP_P CAP_N VNEG CPGND VDD_PLL1 VDD_PLL3 ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 9.4.3. ACS422x68NAG Analog Input Pins Pin Name LIN1 RIN1 LIN2 RIN2 LIN3 DMIC_CLK RIN3 DMIC_DAT Total Pins: 6 9.4.4. ACS422x68NAG Analog Output Pins Pin Name HP_L HP_R Class D L+ Class D L- Class D ...
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ACS422x68 LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC 9.4.6. ACS422x68NAG Clock Pins Pin Name MCLK NC Total Pins: 10 ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. Pin Function I/O Master Clock I(XTAL) No Connect NC Table 100. ACS422x68NAG Clock Pins 89 Internal Pull-up Pin location ...
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... The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0 Note: IDT’s package thicknesses are <2.5mm and <350 mm ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. Figure 36. Package Outline 3 ...
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... The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0 Note: IDT’s package thicknesses are <2.5mm and <350 mm ©2011 INTEGRATED DEVICE TECHNOLOGY, INC. Figure 37. NAG/HLA Package Outline 3 ...
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... ACS422A68TAGyyX ACS422D68TAGyyX ACS422A68NAGyyX ACS422D68NAGyyX yy = silicon revision, contact IDT for current part number. 14. DISCLAIMER While the information presented herein has been checked for both accuracy and reliability, manufac- turer assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...
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... IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. ...