ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 65

• Manufacturer Part Number: ACS422A68TAGZBX8
• Description: Interface - CODECs
• Manufacturer: IDT

Specifications of ACS422A68TAGZBX8

• Rohs: yes
• Part # Aliases: IDTACS422A68TAGZBX8

ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
R20 (14h)
Audio Interface
Control 2
(AIC2)
TRI is used to tri-state the ADCDOUT, ADCLRCK, DACLRCK, ADCBCLK, and DACBCLK pins. In Slave mode (MAS-
TER=0) only ADCDOUT will be tri-stated since the other pins are configured as inputs. The Tri-stated pins are pulled
low with an internal pull-down resistor unless that resistor is disabled.
Although the DAC and ADC interfaces implement separate Bit Clock and LR Clock pins, it is also possible to share one
or both of the clocks.
the following restrictions must be observed when the BCLK from one path (DAC or ADC) is combined with the LRCLK
from the other path (ADC or DAC) as described by the Bit Clock and LR Clock Mode Selection table below:
Register Address
5.7.2.
5.7.3.
Audio Interface Output Tri-state
Audio Interface Bit Clock and LR Clock configuration
1. Both the DAC and ADC must be programmed for the same sample rate
2. Both the DAC and ADC must be programmed for the same number of clocks per frame
3. When in slave mode, the DAC and ADC data must be aligned relative to the provided BCLK and
4. The DAC and ADC must be powered down when changing the BLRCM mode
5. If sharing the BCLK from one path (DAC or ADC) and the LRCLK from the other path (ADC or
7:6
5:4
2:0
Bit
LRCLK (this is guaranteed in master mode)
DAC), shut down both the DAC and ADC before programming the sample rate and clocks per
frame for either. (Again, both must match.)
3
DACDSEL[1:0]
ADCDSEL[1:0]
BLRCM[2:0]
Label
TRI
Table 70. AIC2 Register
Type
RW
RW
RW
RW
Default
000
00
00
65
0
00: left DAC = left I2S data; right DAC = right I2S data
01: left DAC = left I2S data; right DAC = left I2S data
10: left DAC = right I2S data; right DAC = right I2S data
11: left DAC = right I2S data; right DAC = left I2S data
00: left I2S data = left ADC; right I2S data = right ADC
01: left I2S data = left ADC; right I2S data = left ADC
10: left I2S data = right ADC; right I2S data = right ADC
11: left I2S data = right ADC; right I2S data = left ADC
Tri-states ADCDOUT, ADCLRCLK, DACLRCLK,
ADCBCLK, and DACBCLK pins.
0 = ADCDOUT is an output, ADCLRCK, DACLRCLK,
ADCBCLK, and DACBCLK are inputs (slave mode) or
outputs (master mode)
1 = ADCDOUT, ADCLRCK, DACLRCLK, ADCBCLK, and
DACBCLK are high impedance
Bitclock and LRClock mode. See Table Below
Description
ACS422X68
V1.6 01/13