ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 61

no-image

ACS422A68TAGZBX8

Manufacturer Part Number
ACS422A68TAGZBX8
Description
Interface - CODECs
Manufacturer
IDT
Datasheet

Specifications of ACS422A68TAGZBX8

Rohs
yes
Part # Aliases
IDTACS422A68TAGZBX8
ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
R36 (24h)
D-Mic Control
(DMICCTL)
Register Address
4.8.1.
Microphones
DMIC Register
Digital
DMIC_DAT
DMIC_CLK
Bit
6:5
3:2
1:0
7
4
DMPhAdj[1:0]
DMRate[1:0]
Figure 23. Stereo Digital Microphone Configuration
DMicEn
DMono
Multiplexer
RSVD
Label
External
DMIC_CLK
DMIC_DAT
Off-Chip
Channel
Pin
Pin
Table 68. DMICCTL Register
Right
Data R
Valid
Type
RW
RW
RW
RW
R
On-Chip
Channel
Data L
Multiplexer
Valid
Left
On-Chip
Default
61
00
00
00
0
0
Data R
Valid
Digital Microphone Enable
0 = DMIC interface is disabled (DMIC_CLK low,
DMIC muted)
1 = DMIC interface is enabled
Reserved
0 = stereo operation, 1 = mono operation (left
channel duplicated on right)
Selects when the D-Mic data is latched relative to the
DMIC_CLK.
00 = Left data rising edge / right data falling edge
01 = Left data center of high / right data center of low
10 = Left data falling edge / right data rising edge
11 = Left data center of low / right data center of high
Selects the DMIC clock rate: See table in text
Data L
Valid
STEREO
ADC
PCM
Data R
Valid
Description
Stereo Channels
Output
ACS422X68
V1.6 01/13

Related parts for ACS422A68TAGZBX8