ACS422A68TAGZBX8 IDT, ACS422A68TAGZBX8 Datasheet - Page 40
ACS422A68TAGZBX8
Manufacturer Part Number
ACS422A68TAGZBX8
Description
Interface - CODECs
Manufacturer
IDT
Datasheet
1.ACS422A68TAGZBX8.pdf
(93 pages)
Specifications of ACS422A68TAGZBX8
Rohs
yes
Part # Aliases
IDTACS422A68TAGZBX8
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ACS422x68
LOW-POWER, HIGH-FIDELITY, INTEGRATED CODEC
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
•
•
•
PWM Control 1 Register
PWM Control 2 Register
PWM Control 3 Register
3.15. Other Output Capabilities
Each audio analog output can be separately enabled. Disabling outputs serves to reduce power consumption, and is
the default state of the device.
R67 (43h)
PWM1
R68 (44h)
PWM2
R69 (45h)
PWM3
Register Address
Register Address
Register Address
6:2
7:2
7:6
5:0
Bit
Bit
Bit
7
1
0
1
0
pwm_outmode
pwm_outflip
dithpos[4:0]
dvalue[5:0]
cvalue[5:0]
dith_range
outctrl[1:0]
RSVD
dithclr
Label
Label
Label
Table 44. PWM1 Register
Table 45. PWM2 Register
Table 46. PWM3 Register
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
R
Default
Default
Default
0Ah
18h
40
00
0
0
0
0
0
1
Reserved
Dither position, where dither inserted after NS.
0,1,2 = dither bits 2:0
4 = dither bits 3:1
5 = dither bits 4:1
....
19 = dither bits 19:17
1 = dither -1 to +1, 0 = -3 to +3
1 = disable dither
dvalue constant field
1 = swap pwm a/b output pair for all channels
The control lines to the power stage are swapped
inverting the output signal.
1 = tristate, 0 = binary
pwm output muxing
0 = normal
1 = swap 0/1
2 = ch0 on both
3 = ch1 on both
tristate constant field, must be even and not 0
Description
Description
Description
ACS422X68
V1.6 01/13
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