MAX98090AETL+ Maxim Integrated, MAX98090AETL+ Datasheet - Page 84

• Manufacturer Part Number: MAX98090AETL+
• Description: Interface - CODECs 5V 130mW Stereo Headphone Amp
• Manufacturer: Maxim Integrated

Specifications of MAX98090AETL+

• Rohs: yes

MAX98090
Analog Microphone Bias Voltage
The device features a regulated, low noise microphone
bias output (MICBIAS) that can be configured to power
a wide range of external microphone devices. To enable
the microphone bias output, set MBEN in the input enable
register (Table 7). When the device is powered and the
microphone bias is disabled (MBEN is low or the device
is in shutdown), MICBIAS is placed in a high-impedance
state. The microphone bias voltage can be set by the soft-
ware to any one of 4 voltages (2.2V, 2.4V, 2.55V, or 2.8V)
by programming the Microphone Bias Level Configuration
register (Table 11).
Digital Microphone Inputs
One pair of microphone inputs (IN1/IN2) can also be
configured to interface to up to two digital microphones
(Figure 7). The record path DSP is automatically switched
to accept the appropriate digital microphone data channel
when enabled (Figure 13). Both channels (left and right)
must be enabled to use the digital microphone interface.
When both channels are enabled, the digital microphone
interface provides a digital microphone clock on IN2/DMC
Figure 7. Digital Microphone Input Functional Diagram
www.maximintegrated.com
(WLP ONLY)
IN2/DMC
IN1/DMD
MICBIAS
IN3
IN4
IN5
IN6
MIXER
MIXER
RIGHT
MICROPHONE
LEFT
ADC
ADC
MICCLK[2:0]
CONTROL
DIGITAL
MAX98090
RIGHT
LEFT
ADC
ADC
PCLK
DMDR
DMDL
ADCR
ADCL
and accepts PDM data on IN1/DMD. A single digital micro-
phone input cannot be paired with a single analog micro-
phone input. Left channel data is accepted on falling clock
edges while the right channel data is accepted on the rising
clock edges (see Figure 4 for timing requirements).
To avoid any potential clipping and distortion, always
enable the record path DC blocking filters to remove any
built-in DC offsets when using a digital microphone input
(AHPF, Table 21). The record path biquad filter and digital
gain and level control stages can also be applied to digital
microphone input signals.
Digital Microphone Clock Configuration
The digital microphone clock frequency (f
be configured to any one of 6 settings using MICCLK[2:0]
(Table 13). The digital microphone clock is derived from
a PCLK divider, with available settings ranging incremen-
tally from f
digital microphone clock frequencies is intended to sup-
port both current and next generation digital microphones.
Table 12 lists the resulting clock frequencies for common-
ly used master clock (and resulting PCLK) frequencies.
Ultra-Low Power Stereo Audio Codec
DIGITAL
DIGITAL
RIGHT
LEFT
MUX
MUX
MIC
MIC
PCLK
DIGMICR
DIGMICL
TECHNOLOGY
FLEXSOUND
PATH DSP
PATH DSP
/2 to f
RECORD
RECORD
RIGHT
LEFT
DSP
PCLK
/8. This wide range of available
DAI
Maxim Integrated │ 84
DMICCLK
) can