MAX98090AETL+ Maxim Integrated, MAX98090AETL+ Datasheet - Page 155

• Manufacturer Part Number: MAX98090AETL+
• Description: Interface - CODECs 5V 130mW Stereo Headphone Amp
• Manufacturer: Maxim Integrated

Specifications of MAX98090AETL+

• Rohs: yes

Figure 47. START, STOP, and REPEATED START Conditions
MAX98090
I
The MAX98090 features an I
2-wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL
facilitate communication between the MAX98090 and the
master at clock rates up to 400kHz. Figure 3 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus. The master
device writes data to the MAX98090 by transmitting the
proper slave address followed by the register address and
then the data word.
Each transmit sequence is framed by a START (S) or
REPEATED START (Sr) condition and a STOP (P) condi-
tion. Each word transmitted to the MAX98090 is 8 bits long
and is followed by an acknowledge clock pulse. A master
reading data from the MAX98090 transmits the proper
slave address followed by a series of nine SCL pulses.
The MAX98090 transmits data on SDA in sync with the
master-generated SCL pulses. The master acknowl-
edges receipt of each byte of data. Each read sequence
is framed by a START (S) or REPEATED START (Sr)
condition, a not acknowledge, and a STOP (P) condition.
SDA operates as both an input and an open-drain output.
A pullup resistor, typically greater than 500Ω, is required
on SDA. SCL operates only as an input. A pullup resistor,
typically greater than 500Ω, is required on SCL if there are
multiple masters on the bus, or if the single master has an
open-drain SCL output. Series resistors in line with SDA
and SCL are optional. Series resistors protect the digital
inputs of the MAX98090 from high voltage spikes on the
bus lines, and minimize crosstalk and undershoot of the
bus signals.
Table 88. Device I
www.maximintegrated.com
2
C Serial Interface
PART NUMBER
MAX98090A
MAX98090B
READ ADDRESS
2
C Slave Address
0x21
0x23
SDA
SCL
2
C/SMBus-compatible,
WRITE ADDRESS
S
0x20
0x22
Sr
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period of
the SCL pulse. Changes in SDA while SCL is high are con-
trol signals. See the
START and STOP Conditions
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high. A START condition
from the master signals the beginning of a transmission
to the MAX98090. The master terminates transmission,
and frees the bus, by issuing a STOP condition. The bus
remains active if a REPEATED START condition is gener-
ated instead of a STOP condition.
Early STOP Conditions
The MAX98090 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition. For
proper operation, do not send a STOP condition during
the same SCL high pulse as the START condition.
Slave Address
The slave address is defined as the seven most sig-
nificant bits (MSBs) followed by the read/write bit. For the
MAX98090A, the seven most significant bits are 0010000.
Setting the read/write bit to 1 (slave address = 0x21)
configures the MAX98090A for read mode. Setting the
read/write bit to 0 (slave address = 0x20) configures the
MAX98090A for write mode. The address is the first byte
of information sent to the MAX98090 after the START
condition. Similarly, for the MAX98090B, the seven most
significant bits are 0010001. Setting the read/write bit to
1 (slave address = 0x23) configures the MAX98090B for
read mode. Setting the read/write bit to 0 (slave address
= 0x22) configures the MAX98090B for write mode. The
slave address are summarized in Table 88.
Ultra-Low Power Stereo Audio Codec
P
START and STOP Conditions
Maxim Integrated │ 155
section.