MAX98090AETL+ Maxim Integrated, MAX98090AETL+ Datasheet - Page 110

• Manufacturer Part Number: MAX98090AETL+
• Description: Interface - CODECs 5V 130mW Stereo Headphone Amp
• Manufacturer: Maxim Integrated

Specifications of MAX98090AETL+

• Rohs: yes

MAX98090
DAI Digital Audio Data Format
The serial data interface supports multiple pulse code mod-
ulated (PCM) digital audio formats including I
fied, right justified, and time division multiplexed (TDM). If
TDM mode is enabled, it takes precedence and the DAI
data is in TDM format. In this case, all non-TDM digital
audio data format configuration registers have no effect.
Table 46. Digital Audio Interface (DAI) Format Configuration Register
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BIT
7
6
5
4
3
2
1
0
WS[1:0]
ADDRESS: 0x22
NAME
WCI
DLY
BCI
RJ
—
—
TYPE
R/W
R/W
R/W
R/W
R/W
—
—
POR
—
—
0
0
0
0
0
0
Configures the DAI for Right Justified Mode (No Data Delay)
Note: TDM has priority over all other data formats.
Configures the DAI for Frame Clock (LRCLK) Inversion
TDM = 0:
TDM = 1:
Configures the DAI for Bit Clock (BCLK) Inversion
Master Mode:
Configures the DAI for Data Delay (I
Set DLY = 1 to conform to the I
DAI Input Data Word Size
If RJ = 1:
If RJ = 0:
2
S, left justi-
to determine the timing (see the DAI Clock Control and Configuration section for
details).
0: Left justified mode enabled with optional data delay.
1: Right justified mode enabled. DLY register is not used and BSEL[2:0] is used
00: 16 bits
1: SDIN is accepted on the falling edge of BCLK.
0: SDIN is accepted on the rising edge of BCLK.
1: Right-channel data is transmitted while LRCLK is low.
0: Left-channel data is transmitted while LRCLK is low.
1: The most significant bit of an audio word is latched at the second BCLK edge
after the LRCLK transition.
0: The most significant bit of an audio word is latched at the first BCLK edge after
the LRCLK transition.
00: 16 bits
1: LRCLK transitions occur on the rising edge of BCLK.
0: LRCLK transitions occur on the falling edge of BCLK.
0: Start of a new frame is signified by the rising edge of the LRCLK pulse.
1: Start of a new frame is signified by the falling edge of the LRCLK pulse.
If TDM mode is disabled, then the data format is deter-
mined by the configuration selected by the control bits
detailed in Table 46. These settings can be used to
change the DAI data format to several supported stan-
dards such as I
or right justified (Figure 21). In addition, the configuration
settings can be enabled or disabled independently, allow-
ing the device to support many nonstandard data format
variations.
10: 24 bits
01, 10, 11: 20 bits
Ultra-Low Power Stereo Audio Codec
2
S standard. DLY is only effective when TDM = 0.
DESCRIPTION
2
2
S Standard)
01: 20 bits
S (Figure 19), left justified (Figure 20)
—
—
11: Reserved
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