MAX98090AETL+ Maxim Integrated, MAX98090AETL+ Datasheet - Page 160

• Manufacturer Part Number: MAX98090AETL+
• Description: Interface - CODECs 5V 130mW Stereo Headphone Amp
• Manufacturer: Maxim Integrated

Specifications of MAX98090AETL+

• Rohs: yes

MAX98090
Startup/Shutdown Register Sequencing
To ensure proper device initialization and minimal click-
and-pop, program the devices control registers in the
correct order. To shut down the device, simply set
SHDN = 0. Table 89 details an example startup sequence
for the device. To minimize click and pop on the analog
output drivers (headphones, speakers, receiver, and line
outputs), the output drivers should be powered using the
following sequence:
1) Prior to powering the device (SHDN = 0) and before
2) After all configuration settings are complete, power up
3) Enable any analog outputs that are part of the desired
4) Disable the mute on each respective analog output.
Table 89. Detailed Device Startup Sequence
Table 90. Register Changes that Require SHDN = 0
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SEQUENCE
Clock Control Registers
DAC/ADC Enables (only these bits)
Bias/DAC/ADC Control
Digital Signal Processing Coefficients
enabling the outputs, the output driver mute(s) should
be enabled and the PGA gain(s) should be set to their
lowest setting.
the device (SHDN = 1).
configuration.
10
12
11
11
1
2
3
4
5
6
7
8
9
Set SHDN = 0
Configure Clocks (also enable all external clocks)
Configure Digital Audio Interface (DAI)
Configure Digital Signal processing (DSP)
Load Coefficients
Configure Power and Bias Mode
Configure Analog Mixers
Configure Analog Gain and Volume Controls. To Minimize Click
and Pop for Analog Outputs, Enable Mute and Set the Output
PGAs to the minimum gain setting.
Configure Miscellaneous Functions
Set SHDN = 1 (Power Up)
Enable Desired Functions
Disable Mute on Analog Output Drivers
For all Analog Output Drivers, if Gain Smoothing is Disabled
Ramp the Gain up One Volume Step per Write until the Desired
Gain is Reached. If it is Enabled, Program the Desired Gain in a
Single Step.
DESCRIPTION
DESCRIPTION
5) If volume smoothing is disabled (Table 68), ramp the
While many configuration options and settings can be
changed while the device is operating (SHDN = 1),
some settings should only be adjusted with the device
in shutdown (SHDN = 0). Table 90 lists the registers and
bits that should not be changed during active operation.
Changing these settings during normal operation (SHDN
= 1) can compromise device stability and performance
specifications. All external clocks (MCLK in master mode
and MCLK, LRCLK, and BCLK in slave mode) must
be running and stable before the device is taken out of
shutdown. If the clocks are enabled or changed while
the device is active (not in shutdown) phase errors and
audible glitches may be introduced.
Ultra-Low Power Stereo Audio Codec
volume up, one register step at a time, from the mini-
mum setting until the desired volume (gain) is reached
(this sequence is part of the example in Table 81). If
volume smoothing is enabled, this sequence is auto-
matically implemented and the desired volume (gain)
can be programmed in a single step.
0x17 to 0x1A, 0x26 to 0x28, 0x33 to 0x36, 0x41
0x0D, 0x15, 0x16, 0x29, 0x2A, 0x2B, 0x2E,
0x0E to 0x11, 0x2B to 0x2D, 0x30 to 0x32,
0x04, 0x05, 0x1B to 0x20
0x2C, 0x2D, 0x31, 0x32, 0x39, 0x3C
0x03, 0x12, 0x13, 0x14, 0x40
0x46 to 0xBD
0x42 to 0x44
REGISTER
0x3E, 0x3F
0x45 (Default POR State)
0x38, 0x39, 0x3B, 0x3C
0x30 to 0x32, 0x38,
0x39, 0x3B, 0x3C
0x2F, 0x37, 0x3A
0x46 to 0xBD
0x3D to 0x3F
REGISTERS
0x1B to 0x21
0x22 to 0x25
0x42 to 0x44
0x45
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