MAX98090AETL+ Maxim Integrated, MAX98090AETL+ Datasheet - Page 102

• Manufacturer Part Number: MAX98090AETL+
• Description: Interface - CODECs 5V 130mW Stereo Headphone Amp
• Manufacturer: Maxim Integrated

Specifications of MAX98090AETL+

• Rohs: yes

MAX98090
Table 34. System Master Clock (MCLK) Prescaler Configuration Register
Table 35. Master Mode Clock Configuration Register
then no valid clock output is present. In addition to this,
the device does not generate any clocks unless at least
one valid digital audio data path is enabled (ADC record,
DAC playback, digital microphone input, etc.).
In master mode, the device uses two integer values (NI
and MI) as a multiplier and divider (respectively) to scale
PCLK into LRCLK. BCLK is then created either from a
PCLK divider or from an LRCLK multiplier (Table 35).
Based on the oversampling rate selected (OSR, see the
ADC Functional Configuration
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BIT
BIT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
PSCLK[1:0]
BSEL[2:0]
ADDRESS: 0x1B
ADDRESS: 0x21
NAME
NAME
MAS
—
—
—
—
—
—
—
—
—
—
TYPE POR
TYPE POR
R/W
R/W
R/W
—
—
—
—
—
—
—
—
—
—
section), and the config-
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
Master Clock (MCLK) Prescaler Configuration
Master Mode Enable
Bit Clock (BCLK) Configuration (Master Mode/Slave Right Justified Only)
00: Internal master clock generation disabled
01: f
10: f
11: f
0: Slave mode
1: Master mode
000: Bit clock disabled
001: f
010: f
011: f
(LRCLK/BCLK are inputs and accept external clock sources).
(LRCLK/BCLK are outputs and timing signals are generated internally).
PCLK
PCLK
PCLK
BCLK
BCLK
BCLK
= f
= f
= f
= 64 x f
= 32 x f
= 48 x f
MCLK
MCLK
MCLK
/4, 40MHz < f
/1, 10MHz ≤ f
/2, 20MHz < f
S
S
S
ured NI/MI ratio, the output LRCLK frequency is calcu-
lated with the following relationship:
This expression illustrates that in master mode, the rela-
tionship between LRCLK and PCLK frequency (as well as
BCLK) is based on an integer ratio. As a result, any cycle
to cycle jitter or absolute frequency variation in MCLK
is translated first into PCLK and then into LRCLK (and
BCLK) based on the selected clock ratios.
Ultra-Low Power Stereo Audio Codec
MCLK
MCLK
MCLK
DESCRIPTION
DESCRIPTION
100: f
101: f
110: f
111: f
≤ 20MHz
≤ 60MHz
≤ 40MHz
f
LRCLK
BCLK
BCLK
—
—
—
—
—
—
BCLK
BCLK
—
—
—
—
=
= f
= f
= f
= f
PCLK
PCLK
PCLK
PCLK
f
PCLK
/16
/8
/2
/4
×
MI OSR
×
Maxim Integrated │ 102
NI