AT25DQ321-SH-B Adesto Technologies, AT25DQ321-SH-B Datasheet - Page 9

• Manufacturer Part Number: AT25DQ321-SH-B
• Description: Flash 32M 2.7-3.6V, 100Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT25DQ321-SH-B

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 32 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 19 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Factory Pack Quantity: 95

7.
7.1
Read Commands
Read Array
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock signal once the initial starting address has been specified. The device incorporates an internal
address counter that automatically increments on every clock cycle.
Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command. The use of each opcode depends on the
maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock
frequency up to the maximum specified by f
to the maximum specified by f
any clock frequency up to the maximum specified by f
f
To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (1Bh, 0Bh, or 03h)
must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to
specify the starting address location of the first byte to read within the memory array. Following the three address bytes,
additional dummy bytes may need to be clocked into the device depending on which opcode is used for the Read Array
operation. If the 1Bh opcode is used, then two dummy bytes must be clocked into the device after the three address
bytes. If the 0Bh opcode is used, then a single dummy byte must be clocked in after the address bytes.
After the three address bytes (and the dummy bytes or byte if using opcodes 1Bh or 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a byte
first. When the last byte (3FFFFFh) of the memory array has been read, the device will continue reading back at the
beginning of the array (000000h). No delays will be incurred when wrapping around from the end of the array to the
beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can
be deasserted at any time and does not require that a full byte of data be read.
Figure 7-1. Read Array – 1Bh Opcode
CLK
SCK
should be reserved to systems employing the RapidS protocol.
SO
CS
SI
High-impedance
MSB
0
0
0
1
0
2
Opcode
1
3
1
4
RDLF
0
5
1
6
. The 1Bh opcode allows the highest read performance possible and can be used at
1
7
MSB
A
8
A
9
A
Address Bits A23-A0
10 11
CLK
A
A
12
, and the 03h opcode can be used for lower frequency read operations up
A
A
MAX
29 30
A
; however, use of the 1Bh opcode at clock frequencies above
A
31 32
MSB
X
X
33
X
34
Don't Care
X
35
X
36
X
37 38
X
X
39
MSB
X
40
X
41
X
42 43
AT25DQ321 [DATASHEET]
Don't Care
X
X
44
X
45
X
46
X
47 48
MSB
D
8718D–DFLASH–12/2012
D
49
D
Data Byte 1
50 51
D
D
52
D
53
D
54
D
55 56
MSB
D
D
9