AT25DQ321-SH-B Adesto Technologies, AT25DQ321-SH-B Datasheet - Page 25

• Manufacturer Part Number: AT25DQ321-SH-B
• Description: Flash 32M 2.7-3.6V, 100Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT25DQ321-SH-B

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 32 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 19 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Factory Pack Quantity: 95

9.2
Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the Logical 0
state. With the WEL bit reset, all Byte/Page Program, Erase, Protect Sector, Unprotect Sector, Sector Lockdown, Freeze
Sector Lockdown State, Program OTP Security Register, Write Status Register, and Write Configuration Register
commands will not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to the
WEL bit section of the Status Register description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the
device. No address bytes need to be clocked into the device and any data clocked in after the opcode will be ignored.
When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a Logical 0. The complete opcode
must be clocked into the device before the CS pin is deasserted and the CS pin must be deasserted on a byte boundary
(multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change.
Figure 9-2. Write Disable
SCK
SO
CS
SI
MSB
High-impedance
0
0
0
1
0
2
Opcode
0
3
0
4
1
5
0
6
0
7
AT25DQ321 [DATASHEET]
8718D–DFLASH–12/2012
25