AT25DQ321-SH-B Adesto Technologies, AT25DQ321-SH-B Datasheet - Page 17

• Manufacturer Part Number: AT25DQ321-SH-B
• Description: Flash 32M 2.7-3.6V, 100Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT25DQ321-SH-B

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 32 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 19 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Factory Pack Quantity: 95

8.3
Quad-Input Byte/Page Program
The Quad-Input Byte/Page Program command is similar to the Dual-Input Byte/Page Program command and can be
used to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory locations.
Unlike the Dual-Input Byte/Page Program command, the Quad-Input Byte/Page Program command allows four bits of
data to be clocked into the device on every clock cycle rather than two.
Before the Quad-Input Byte/Page Program command can be started, the Write Enable command must have been
previously issued to the device
Register to a Logical 1 state. To perform a Quad-Input Byte/Page Program command, an opcode of 32h must be
clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin
programming at. After the address bytes have been clocked in, data can then be clocked into the device four bits at a
time on the I/O
The data is always input with the MSB of a byte first, and the MSB is always input on the I/O
cycle, bit 7 of the first data byte would be input on the I/O
on the I/O
input on the I/O
after every two clock cycles. Like the standard Byte/Page Program and Dual-Input Byte/Page Program commands, all
data clocked into the device is stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on a 256-byte page boundary (A7-A0 are not all 0), then
special circumstances regarding which memory locations to be programmed will apply. In this situation, any data that is
sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page.
Example:
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data bytes
sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will
not be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed
and should take place in a time of t
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is
deasserted and the CS pin must be deasserted on byte boundaries (multiples of eight bits); otherwise, the device will
abort the operation and no data will be programmed into the memory array. In addition, if the address specified by
A23-A0 points to a memory location within a sector that is in the protected state
locked down
executed and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status
Register will be reset back to the Logical 0 state if the program cycle aborts due to an incomplete address being sent, an
incomplete byte of data being sent, the CS pin being deasserted on non-byte boundaries or because the memory
location to be programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster
throughput, it is recommended that the Status Register be polled rather than waiting the t
data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status
Register will be reset back to the Logical 0 state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program
properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
2
, I/O
If the starting address denoted by A23-A0 is 0000FEh and three bytes of data are sent to the device, then
the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of
data will be programmed at address 000000h. The remaining bytes in the page (addresses 000001h
through 0000FDh) will not be programmed and will remain in the erased state (FFh). In addition, if more
than 256 bytes of data are sent to the device, then only the last 256 bytes sent will be latched into the
internal buffer.
(See “Sector Lockdown” on page
3-0
1
3
, and I/O
, I/O
pins.
2
, I/O
0
1
pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the first data byte would be
, and I/O
(See “Write Enable” on page
0
PP
pins, respectively. The sequence would continue with each byte of data being input
or t
BP
if only programming a single byte.
32), then the Quad-Input Byte/Page Program command will not be
3
pin while bits 6, 5, and 4 of the same data byte would be input
24) to set the Write Enable Latch (WEL) bit of the Status
(See “Protect Sector” on page
AT25DQ321 [DATASHEET]
BP
or t
3
pin. During the first clock
PP
8718D–DFLASH–12/2012
time to determine if the
26) or
17