AT25DQ321-SH-B Adesto Technologies, AT25DQ321-SH-B Datasheet - Page 45

• Manufacturer Part Number: AT25DQ321-SH-B
• Description: Flash 32M 2.7-3.6V, 100Mhz Serial Flash
• Manufacturer: Adesto Technologies

Specifications of AT25DQ321-SH-B

• Rohs: yes
• Data Bus Width: 8 bit
• Memory Type: Flash
• Memory Size: 32 Mbit
• Architecture: Flexible, Uniform Erase
• Timing Type: Synchronous
• Interface Type: SPI
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 19 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Factory Pack Quantity: 95

11.4
Read Configuration Register
The non-volatile Configuration Register can be read to determine if the Quad-Input Byte/Page Program and Quad-Output
Read Array commands have been enabled. Unlike the Status Register, the Configuration Register can only be read
when the device is in an idle state (when the RDY/BSY bit of the Status Register indicates that the device is in a ready
state).
To read the Configuration Register, the CS pin must first be asserted and the opcode of 3Fh must be clocked into the
device. After the opcode has been clocked in, the device will begin outputting the one byte of Configuration Register
data on the SO pin during subsequent clock cycles. The data being output will be a repeating byte as long as the CS pin
remains asserted and the clock pin is being pulsed.
At clock frequencies above f
above f
Configuration Register.
Deasserting the CS pin will terminate the Read Configuration Register operation and put the SO pin into a
high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
The Configuration Register is a non-volatile register; therefore, the contents of the Configuration Register are not
affected by power cycles or power-on reset operations.
Table 11-5. Configuration Register Format
Notes: 1.
Bit
6:0
7
(1)
CLK
2.
Name
RES
, at least two bytes of data must be clocked out from the device in order to determine the correct value of the
QE
Only bit 7 of the Configuration Register will be modified when using the Write Configuration Register
command.
R/W = Readable and Writeable
R = Readable only
Quad Enable
Reserved for Future Use
CLK
, the first byte of data output will not be valid. Therefore, if operating at clock frequencies
Type
R/W
R
(2)
Description
0
1
0
Quad-Input/Output commands and operation disabled.
Quad-Input/Output commands and operation enabled.
(WP and HOLD disabled)
Reserved for future use.
AT25DQ321 [DATASHEET]
8718D–DFLASH–12/2012
45