XRT91L30ES Exar, XRT91L30ES Datasheet - Page 30

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XRT91L30ES

Manufacturer Part Number
XRT91L30ES
Description
Bus Transceivers
Manufacturer
Exar
Datasheet

Specifications of XRT91L30ES

Product Category
Bus Transceivers
Rohs
yes
XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
Table 16
CDR or an external recovered clock in loop timing applications is shown in
F
IGURE
CDRDIS
16. L
0
0
1
1
provides configuration for selecting the loop timing and clock recovery modes. The use of the on-chip
OOP
RXDO[7:0]
RXPCLKO
TTLREFCLK
T
LOOPTIME
TXDI[7:0]
REFCLKP
REFCLKN
TXPCLK_IO
PIO_CTRL
IMING
CDRDIS
LOOPTIME
T
ABLE
~ ~
M
ENB
ODE
0
1
0
1
Div by 8
ENB
16: L
8
U
0
1
8
SING
OOP
Div by
SIPO
155.52MHz
8
622.08/
I
CMU
NTERNAL
PISO
T
External CDR thru XRXCLKIP/N
IMING AND
T
RANSMIT
DATA
CLK
Clock Multiplier Unit
Clock Multiplier Unit
MUX
Internal CDR
CDR
XRT91L30
C
C
LOCK
LOCK
26
DATA
OR AN
CLK
S
Clk
Data
OURCE
to Retimer
R
E
CDR
ECOVERY CONFIGURATIONS
XTERNAL
Retimer
622.08/155.52 Mbps data on RXIP/N sampled at
622.08/155.52 Mbps data on RXIP/N sampled at
R
Clock and Data recovery by internal CDR
Clock and Data recovery by internal CDR
Externally recovered Receive Clock from
Externally recovered Receive Clock from
ECOVERED
~ ~
Figure
XRXCLKIP
XRXCLKIN
RXIP
RXIN
TXOP
TXON
rising edge of XRXCLKIP/N
rising edge of XRXCLKIP/N
R
ECEIVE
16.
CDR Disabled.
CDR Disabled.
CDR Enabled.
CDR Enabled.
C
XRXCLKIP/N
XRXCLKIP/N
LOCK
C
LOCK
S
OURCE
REV. 1.0.2

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