XRT91L30ES Exar, XRT91L30ES Datasheet - Page 20

• Manufacturer Part Number: XRT91L30ES
• Description: Bus Transceivers
• Manufacturer: Exar

Specifications of XRT91L30ES

• Product Category: Bus Transceivers
• Rohs: yes

XRT91L30
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock.
Asserting the CDRDIS "High" disables the internal Clock and Data Recovery unit and the received serial data
bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of the externally recovered
differential clock XRXCLKIP/N coming from the optical module or an external clock recovery unit.
shows the possible internal paths of the recovered clock and data.
These 0.47 F non-polarized external loop filter capacitors provide the necessary components to achieve the
required receiver jitter performance. They must be well isolated to prohibit noise entering the CDR block and
should be placed as close to the pins as much as possible.
loop filter components. These two non-polarized capacitors should be of +/- 10% tolerance.
XRT91L30 supports internal Loss of Signal detection (LOS) and external LOS detection. The internal Loss of
Signal Detector monitors the incoming data stream and if the incoming data stream has no transition
continuously for more than 128 bit periods, Loss of Signal is declared. This LOS detection will be removed
when the circuit detects 16 transitions in a 128 bit period sliding window. Pulling the corresponding DLOSDIS
signal to a high level will disable the internal LOS detection circuit. The external LOS function is supported by
the LOSEXT input. The Single-Ended LVPECL input usually comes from the optical module through an output
usually called “SD” or “FLAG” which indicates the lack or presence of optical power. Depending on the
manufacturer of these devices the polarity of this signal can be either active "Low" or active "High." LOSEXT is
an active "Low" signal requiring a low level to assert or invoke a forced LOS. The external LOSEXT input pin
and internal LOS detector are gated to control detection and declaration of Loss of Signal (see figure 7).
Whenever LOS is internally detected or an external LOS is asserted thru the LOSEXT pin, the XRT91L30 will
automatically force the receive parallel data output to a logic state "0" for the entire duration that a LOS
F
F
2.4
2.5
2.3.1
IGURE
IGURE
Parallel DATA
Div by 8 CLOCK
5. I
6. E
External Receive Loop Filter Capacitors
Loss Of Signal
CDRDIS
Internal Clock and Data Recovery Bypass
NTERNAL
XTERNAL
pin 39
8
C
L
CAP1P
LOCK AND
OOP
F
ILTERS
non-polarized
0.47uF
D
SIPO
ATA
R
CAP2P
ECOVERY
pin 42
CLOCK
DATA
B
YPASS
16
pin 40
CAP1N
Figure 6
non-polarized
Clk
Data
0.47uF
CDR
shows the pin connections and external
CAP2N
pin 41
XRXCLKIP
XRXCLKIN
RXIP
RXIN
REV. 1.0.2
Figure 5