XRT91L30ES Exar, XRT91L30ES Datasheet - Page 27

• Manufacturer Part Number: XRT91L30ES
• Description: Bus Transceivers
• Manufacturer: Exar

Specifications of XRT91L30ES

• Product Category: Bus Transceivers
• Rohs: yes

REV. 1.0.2
To decouple transmit parallel clock domains of the framer/mapper device and the XRT91L30 transceiver and to
eliminate difficult timing issues between them, the transmit parallel clock TXPCLK_IO can also be optionally
configured as a clock input. Rather than provide a transmit parallel clock output reference to the framer/mapper
device, the XRT91L30 can instead accept a reference transmit parallel clock input signal from the framer/
mapper device to sample the transmit parallel bus. When PIO_CTRL pin 48 is asserted "Low," TXPCLK_IO
switches into a clock input and the XRT91L30 will now sample data on the transmit parallel bus TXDI[7:0]
based on TXPCLK_IO clock input reference coming from the framer/mapper device. The use of the alternate
transmit parallel bus clock input option permits the system to tolerate an arbitrary amount of phase mismatch
and jitter between framer/mapper transmit parallel clock timing and transceiver transmit timing.
provides a detailed overview of the alternate transmit parallel bus clock input system interface.
When applying parallel data input to the transmitter in the alternate transmit parallel bus clock input mode of
operation, the setup and hold times should be followed as shown in
F
F
3.3
3.4
IGURE
IGURE
Transmit Parallel
Framer/Mapper
Clock driven by
TXPCLK_IO
TXDI[7:0]
14. A
13. A
Alternate Transmit Parallel Bus Clock Input Option
Alternate Transmit Parallel Data Input Timing
Device
LTERNATE
LTERNATE
T
T
RANSMIT
RANSMIT
SONET Framer/ASIC
P
P
ARALLEL
ARALLEL
Alternate Transmit Parallel Clock Input Option
t
TXDI_SU
I
I
NPUT
NPUT
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
TXDI[7:0]
TXPCLK_IO
(Parallel Clock Input Option)
t
TXPCLK_IO
T
I
NTERFACE
IMING
8
23
B
PIO_CTRL
LOCK
TTLREFCLK
Figure 14
(P
STS-12/STM-4
t
STS-3/STM-1
TXDI_HD
Transceiver
XRT91L30
ARALLEL
REFCLKP
or
REFCLKN
CMUFREQSEL
and
C
LOCK
Table
I
NPUT
13,
Table
O
PTION
XRT91L30
14.
Figure 13
)