XRT91L30ES Exar, XRT91L30ES Datasheet
XRT91L30ES
Specifications of XRT91L30ES
Related parts for XRT91L30ES
XRT91L30ES Summary of contents
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JUNE 2007 Rev. 1.0.2 Network & Transmission Products STS-12/STM-4 or STS-3/STM-1 SONET/SDH TRANSCEIVER XRT91L30 ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER NOTES: II REV. 1.0.2 ...
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REV. 1.0.2 NOTES:..................................................................................................................................................... ............................................................................................................ ABLE OF ONTENTS GENERAL DESCRIPTION................................................................................................. 1 APPLICATIONS........................................................................................................................................... XRT91L30 ...................................................................................................................................... 1 IGURE LOCK IAGRAM OF ..................................................................................................................................................... 2 FEATURES QFP P O XRT91L30 (T IGURE IN UT ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER F 14 IGURE LTERNATE RANSMIT ARALLEL T 13 ABLE LTERNATE RANSMIT ARALLEL T 14 ABLE LTERNATE RANSMIT ARALLEL 3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT ...
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... SONET/SDH Test Equipment DWDM Termination Equipment STS-12/STM-4 or STS-3/STM-1 TRANSCEIVER PISO Re-Timer (Parallel Input Serial Output) 8 CMU RLOOPS DLOOP SIPO CDR Control Block • • (510) 668-7000 FAX (510) 668-7017 XRT91L30 REV. 1.0.2 TXOP/N ALOOP RXIP/N XRXCLKIP/N Clock Control • www.exar.com ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER FEATURES Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08 Mbps or STS-3/STM-1 155.52 Mbps Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit ...
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REV. 1.0 QFP P IGURE 49 AGND 50 49 TXPCLK_IO FL1 51 50 TXDI7 STS1_1 52 51 TXDI6 MCLK_1 53 52 GND GND 54 53 TXDI5 RCLK_1 55 54 TXDI4 RPOS_1 56 55 TXDI3 RNEG_1 57 56 ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER PIN DESCRIPTIONS HARDWARE CONTROL AME EVEL RESET LVTTL, LVCMOS STS12/STS3 LVTTL, LVCMOS CMUFREQSEL LVTTL, LVCMOS P YPE Master Reset Input Active "High." When this pin is pulled "High" ...
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REV. 1.0 AME EVEL CDRREFSEL LVTTL, LVCMOS LOOPTIME LVTTL, LVCMOS CDRDIS LVTTL, LVCMOS PIO_CTRL LVTTL, LVCMOS STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER P YPE Clock and Data Recover Unit Reference Frequency Select Selects the Clock ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER AME EVEL RLOOPS LVTTL, LVCMOS DLOOP LVTTL, LVCMOS ALOOP LVTTL, LVCMOS P YPE Serial Remote Loopback The serial remote loopback mode interconnects the receive serial data input to ...
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REV. 1.0.2 TRANSMITTER SECTION AME EVEL TXDI0 LVTTL, TXDI1 LVCMOS TXDI2 TXDI3 TXDI4 TXDI5 TXDI6 TXDI7 TXOP LVPECL Diff TXON TXPCLK_IO LVTTL, LVCMOS STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER P YPE Transmit Parallel Data Input ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER TRANSMITTER SECTION AME EVEL REFCLKP LVPECL Diff REFCLKN TTLREFCLK LVTTL, LVCMOS P YPE Reference Clock Input (77.76 MHz or 19.44 MHz) 17 This differential clock input reference is ...
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REV. 1.0.2 RECEIVER SECTION AME EVEL RXDO0 LVTTL, RXDO1 LVCMOS RXDO2 RXDO3 RXDO4 RXDO5 RXDO6 RXDO7 RXIP Diff LVPECL RXIN XRXCLKIP Diff LVPECL XRXCLKIN RXPCLKO LVTTL, LVCMOS CDRAUX- LVTTL, REFCLK LVCMOS OOF LVTTL, LVCMOS FRAMEPULSE LVTTL, LVCMOS ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER AME EVEL CAP1P Analog CAP2P CAP1N Analog CAP2N DLOSDIS LVTTL, LVCMOS LOSEXT SE-LVPECL POWER AND GROUND N T AME YPE VDD3.3 PWR 15, 18, 31, 34, 47, 61 AVDD3.3_TX PWR AVDD3.3_RX ...
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REV. 1.0 AME YPE AGND_RX PWR GND GND 21, 28, 35, 45, 46, 52 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER Receiver Analog Ground for 3.3V Analog Power Supplies It is recommended that all ground pins of ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 1.0 FUNCTIONAL DESCRIPTION The XRT91L30 transceiver is designed to operate with a SONET Framer/ASIC device and provide a high- speed serial interface to optical networks. The transceiver converts 8-bit parallel data running at 77.76 ...
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REV. 1.0.2 2.0 RECEIVE SECTION The receive section of XRT91L30 include the inputs RXIP/N, followed by the clock and data recovery unit (CDR) and receive serial-to-parallel converter. The receiver accepts the high speed Non-Return to Zero (NRZ) serial data at ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.2 Recieve Serial Data Input Timing The received High-Speed Serial Differential Data Input must adhere to the set-up and hold time timing specifications below IGURE ECEIVE IGH PEED ...
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REV. 1.0.2 2.3 Receive Clock and Data Recovery The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential LVPECL receiver and generates a clock that is the same frequency as the incoming data. ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 2.3.1 Internal Clock and Data Recovery Bypass Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock. Asserting the CDRDIS "High" disables the internal Clock and Data ...
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REV. 1.0.2 condition is declared. This acts as a receive data mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data LOS D IGURE ECLARATION CIRCUIT Intern etect ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER bit de-interleaves the serial data input into an 8-bit parallel output to RXDO[7:0]. A simplified block diagram is shown in Figure 8. XRT91L30 clocks data out on RXDO[7:0] at the falling edge of RXPCLKO. ...
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REV. 1.0.2 2.10 Receive Parallel Data Output Timing The receive parallel data output from the STS-12/STM-4 or STS-3/STM-1 receiver will adhere to the setup and hold times shown in Figure 10 ,Table specifications IGURE ECEIVE ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER T 10: PECL ABLE S YMBOL t PECL output rise time (20% to 80%) R_PECL t PECL output fall time (80% to 20%) F_PECL t TTL output rise time (10% to 90%) R_TTL t ...
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REV. 1.0.2 3.0 TRANSMIT SECTION The transmit section of the XRT91L30 accepts 8-bit parallel data and converts it to serial Differential LVPECL data output intented to interface to an optical module. It consists of an 8-bit parallel Single-Ended LVTTL interface, ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 3.2 Transmit Parallel Data Input Timing When applying parallel data input to the transmitter, the setup and hold times should be followed as shown in Figure 12 and Table 11, Table 12. F 12. ...
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REV. 1.0.2 3.3 Alternate Transmit Parallel Bus Clock Input Option To decouple transmit parallel clock domains of the framer/mapper device and the XRT91L30 transceiver and to eliminate difficult timing issues between them, the transmit parallel clock TXPCLK_IO can also be ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER T 13 ABLE LTERNATE RANSMIT S YMBOL t Transmit Clock Input period TXPCLK_IO t Transmit data setup time with respect to TXPCLK_IO TXDI_SU t Transmit data hold time with respect to TXPCLK_IO ...
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REV. 1.0.2 3.6 Clock Multiplier Unit (CMU) and Re-Timer The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS- 12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH transmit serial data rate ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER Table 16 provides configuration for selecting the loop timing and clock recovery modes. The use of the on-chip CDR or an external recovered clock in loop timing applications is shown in T 16: L ...
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REV. 1.0.2 3.8 Transmit Serial Output Control The 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/STM-1 transmit serial output is avaliable on TXOP/N pins. The transmit serial output can coupled to an optical module or electrical interface. ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 4.0 DIAGNOSTIC FEATURES 4.1 Serial Remote Loopback The serial remote loopback function is activated by setting RLOOPS "High". When serial remote loopback is activated, the high-speed serial receive data from RXIP/N is presented at ...
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REV. 1.0.2 4.3 Analog Local Loopback Analog Local Loopback (ALOOP) controls a more comprehensive version of digital local loopback in which the point where the transmit data is looped back is moved all the way back to the high-speed receive ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER 4.5 Eye Diagram The XRT91L30 Eye diagram illustrates the transmit serial output signal integrity and quality IGURE RANSMIT LECTRICAL STS-3/STM-1 4.6 SONET Jitter Requirements SONET equipment jitter requirements are ...
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REV. 1.0.2 F 23. GR-253 J T IGURE ITTER OLERANCE A 3 Input Jitter Amplitude ( OC-N/STS-N LEVEL T 17: XRT91L30 R ABLE F B REQUENCY AND I NTERFACE (KH ) ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER F 25. XRT91L30 M IGURE EASURED STS-3/STM-1 4.6.2 Jitter Generation Jitter generation is defined as the amount of jitter at the STS-N output in the absence of applied input jitter. The bandwidth is set ...
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REV. 1.0.2 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Thermal Resistance of QFP Package........ Thermal Resistance of QFP Package........ ESD Protection (HBM)..........................................>2000V ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS S T YMBOL YPE VDD CMOS Digital Power Supply 3.3 VDD PECL I/O ...
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XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS Test Conditions: VDD = 3. unless otherwise specified YMBOL YPE ARAMETER V LVPECL Output High Voltage OH V LVPECL Output Low ...
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REV. 1.0 ART UMBER XRT91L30IQ 64-pin Plastic Quad Flat Pack (10.0 x 10.0 x 2.0 mm, QFP) PACKAGE DIMENSIONS Note: The control dimension is in millimeters. SYMBOL STS-12/STM-4 OR ...
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... June 2007 Minor editorial changes, Minor changes to figure 3,15 and 17 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...