XRT91L30ES Exar, XRT91L30ES Datasheet - Page 29

• Manufacturer Part Number: XRT91L30ES
• Description: Bus Transceivers
• Manufacturer: Exar

Specifications of XRT91L30ES

• Product Category: Bus Transceivers
• Rohs: yes

REV. 1.0.2
The clock synthesizer uses a 77.76 MHz or a 19.44 MHz reference clock to generate the 622.08 MHz (for STS-
12/STM-4) or 155.52 MHz (for STS-3/STM-1) SONET/SDH transmit serial data rate frequency. Differential
LVPECL input REFCLKP/N accepts a clock reference of 77.76 MHz or 19.44 MHz to synthesize a high speed
622.08 MHz clock for STS-12/STM-4 or 155.52 MHz clock for STS-3/STM-1 applications. Optionally, if a
Differential LVPECL clock source is not available, TTLREFCLK can accept an LVTTL clock signal. The clock
synthesizer uses a PLL to lock-on to the differential input REFCLKP/N or Single-Ended input TTLREFCLK
reference clock. The REFCLKP/N input should be generated from an LVPECL crystal oscillator which has a
frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the necessary
accuracy required for SONET systems. If the TTLREFCLK
reference input should be tied to a LVTTL crystal oscillator with 20ppm accuracy. The two reference clocks are
XNOR’ed and the choice between the LVPECL and LVTTL clocks are controlled tying either REFCLKP or
TTLREFCLK to ground. Table 1 shows the CMU reference clock frequency settings.
Clock Multiplier Unit’s requirements for the Reference clock.
Two types of loop timing are possible in the XRT91L30.
In the internal loop timing mode, loop timing is controlled by the LOOPTIME pin. This mode is selected by
asserting the LOOPTIME signal to a high level. When the loop timing mode is activated, the CMU synthesized
hi-speed reference clock input to the Retimer is replaced with the hi-speed internally recovered receive clock
coming from the CDR. Under this condition both the transmit and receive sections are synchronized to the
internally recovered receive clock. Loop time mode directly locks the Retimer to the recovered receive clock.
In external loop timing mode, the XRT91L30 allows the user the flexibility of using an externally recovered
receive clock for retiming the high speed serial data. First, the CDRDIS input pin should be set high. By doing
so, the internal CDR is disabled and bypassed and the XRT91L30 will sample the incoming high speed serial
data on RXIP/N with the externally recovered receive clock connected to the XRXCLKIP/N inputs. In this state,
the receive clock de-jittering and recovery is done externally and fed thru XRXCLKIP/N and the XRT91L30 will
sample RXIP/N on the rising edge of XRXCLKIP/N. Secondly, the LOOPTIME pin must also be set high in
order to select the externally recovered receive clock on XRXCLKIP/N as the reference clock source for the
transmit serial data output stream TXOP/N.
REF
REF
REF
REF
3.6
3.7
N
DUTY
JIT
JIT
TOL
Jitter specification is defined using a 12kHz to 1.3/5MHz LP-HP single-pole filter.
1
2
These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUI
Required to meet SONET output frequency stability requirements.
AME
Clock Multiplier Unit (CMU) and Re-Timer
Loop Timing and Clock Control
Reference clock duty cycle
Reference clock jitter (rms) with 19.44 MHz reference
Reference clock jitter (rms) with 77.76 MHz reference
Reference clock frequency tolerance
T
ABLE
15: C
LOCK
P
M
ARAMETER
ULTIPLIER
2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
U
25
NIT
1
1
’
S
R
EQUIREMENTS FOR
reference clock is used, the TTLREFCLK
R
M
-20
40
IN
EFCLK
Table 15
T
YP
M
+20
60
13
XRT91L30
5
specifies the
AX
rms
).
U
ppm
NITS
%
ps
ps