LPC1317FHN33,551 NXP Semiconductors, LPC1317FHN33,551 Datasheet - Page 54

• Manufacturer Part Number: LPC1317FHN33,551
• Description: ARM Microcontrollers - MCU 32bit ARM Cortex-M3 64KB Flash 10KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1317FHN33,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC1317
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 72 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 15.
T
[1]
[2]
[3]
[4]
[5]
[6]
[7]
LPC1315_16_17_45_46_47
Product data sheet
Symbol
f
t
t
t
t
t
SCL
f
LOW
HIGH
HD;DAT
SU;DAT
amb
See the I
Parameters are valid over operating temperature range unless otherwise specified.
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V
bridge the undefined region of the falling edge of SCL.
C
The maximum t
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified t
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
=
b

= total capacitance of one bus line in pF.
40

Dynamic characteristic: I
C to +85
2
C-bus specification UM10204 for details.
10.4 I/O pins
10.5 I
Parameter
SCL clock
frequency
fall time
LOW period of the
SCL clock
HIGH period of the
SCL clock
data hold time
data set-up time
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t

C.
[2]
Table 14.
T
[1]
Symbol
t
t
2
amb
r
f
C-bus
Applies to standard port pins and RESET pin.
=

40

Dynamic characteristics: I/O pins
Parameter
rise time
fall time
C to +85
[4][5][6][7]
[3][4][8]
[9][10]
2
C-bus pins
All information provided in this document is subject to legal disclaimers.
f
.

C; 3.0 V
Rev. 3 — 20 September 2012
Conditions
Standard-mode
Fast-mode
Fast-mode Plus
of both SDA and SCL
signals
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
Standard-mode
Fast-mode
Fast-mode Plus
[1]
Conditions
pin configured as output
pin configured as output
Standard-mode
Fast-mode
Fast-mode Plus

V
DD

3.6 V.
LPC1315/16/17/45/46/47
[1]
Min
0
0
0
-
20 + 0.1  C
-
4.7
1.3
0.5
4.0
0.6
0.26
0
0
0
250
100
50
32-bit ARM Cortex-M3 microcontroller
Min
3.0
2.5
b
Typ
-
-
IH
(min) of the SCL signal) to
Max
100
400
1
300
300
120
-
-
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2012. All rights reserved.
Max
5.0
5.0
f
is specified at
Unit
kHz
kHz
MHz
ns
ns
ns
s
s
s
s
s
s
s
s
s
ns
ns
ns
ns
54 of 77
Unit
ns