LPC1317FHN33,551 NXP Semiconductors, LPC1317FHN33,551 Datasheet - Page 17

• Manufacturer Part Number: LPC1317FHN33,551
• Description: ARM Microcontrollers - MCU 32bit ARM Cortex-M3 64KB Flash 10KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1317FHN33,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC1317
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 72 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
Table 3.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
LPC1315_16_17_45_46_47
Product data sheet
Symbol
VREFP
V
V
V
SSA
DD
SS
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.
See
reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down
mode.
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see
I
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see
includes high-current output driver.
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see
programmable digital input glitch filter.
WAKEUP pin. 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and
analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see
includes digital input glitch filter.
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
2
C-bus pins compliant with the I
Figure 33
Pin description (LPC1315/16/17 - no USB)
for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
64
55
10;
33;
58
7;
54
2
C-bus specification for I
-
-
8;
44
5;
41
-
-
6;
29
33
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 September 2012
-
-
-
-
2
C standard mode, I
-
-
-
-
Description
ADC positive reference voltage: This should be nominally
the same voltage as V
minimize noise and error. Level on this pin is used as a
reference for ADC. This pin should be tied to 3.3 V if the
ADC is not used.
Analog ground: 0 V reference. This should nominally be
the same voltage as V
isolated to minimize noise and error.
Supply voltage to the internal regulator and the external
rail. On LQFP48 and HVQFN33 packages, this pin is also
connected to the 3.3 V ADC supply and reference
voltage.
Ground.
LPC1315/16/17/45/46/47
2
C Fast-mode, and I
32-bit ARM Cortex-M3 microcontroller
SS
DDA
Product data sheet but should be
2
C Fast-mode Plus.
but should be isolated to
Figure
© NXP B.V. 2012. All rights reserved.
32); includes
Figure
Figure
Figure
32);
17 of 77
32);
32).