LPC1317FHN33,551 NXP Semiconductors, LPC1317FHN33,551 Datasheet - Page 28

• Manufacturer Part Number: LPC1317FHN33,551
• Description: ARM Microcontrollers - MCU 32bit ARM Cortex-M3 64KB Flash 10KB SRAM
• Manufacturer: NXP Semiconductors

Specifications of LPC1317FHN33,551

• Rohs: yes
• Core: ARM Cortex M3
• Processor Series: LPC1317
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 72 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 2 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: HVQFN-33
• Mounting Style: SMD/SMT
• Factory Pack Quantity: 260

NXP Semiconductors
LPC1315_16_17_45_46_47
Product data sheet
7.10.1 Features
7.11.1 Features
7.12 I
7.11 SSP serial I/O controller
The USART includes full modem control, support for synchronous mode, and a smart
card interface. The RS-485/9-bit mode allows both software address detection and
automatic address detection using 9-bit mode.
The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
The SSP controllers are capable of operation on a SSP, 4-wire SSI, or Microwire bus. It
can interact with multiple masters and slaves on the bus. Only a single master and a
single slave can communicate on the bus during a given data transfer. The SSP supports
full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
The LPC1315/16/17/45/46/47 contain one I
The I
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
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C-bus serial I/O controller
Maximum USART data bit rate of 3.125 Mbit/s.
16-byte receive and transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
Support for RS-485/9-bit mode.
Support for modem control.
Support for synchronous mode.
Includes smart card interface (ISO 7816-3).
Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
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C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 20 September 2012
LPC1315/16/17/45/46/47
2
C-bus controller.
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2012. All rights reserved.
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