C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 252
C8051F966-A-GQ
Manufacturer Part Number
C8051F966-A-GQ
Description
8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F966-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
32 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
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C8051F96x
18.6. Minimizing Flash Read Current
The flash memory in the C8051F96x devices is responsible for a substantial portion of the total digital sup-
ply current when the device is executing code. Below are suggestions to minimize flash read current.
252
1. Use idle, low power idle, suspend, or sleep modes while waiting for an interrupt, rather than polling
2. The flash memory is organized in 4-byte words starting with a byte with address ending in 00b and
3. To minimize the power consumption of small loops, it is best to locate them such that the number of
the interrupt flag. Idle mode and low power idle mode is particularly well-suited for use in
implementing short pauses, since the wake-up time is no more than three system clock cycles. See
the Power Management chapter for details on the various low-power operating modes.
ending with a byte with address ending in 11b. A 4-byte pre-fetch buffer is used to read 4 bytes of
flash in a single read operation. Short loops that straddle word boundaries or have an instruction byte
with address ending in 11b should be avoided when possible. If a loop executes in 20 or more clock
cycles, any resulting increase in operating current due to mis-alignment will be negligible.
4-byte words to be fetched from flash is minimized. Consider a 2-byte, 3-cycle loop (e.g., SJMP $, or
while(1);). The flash read current of such a loop will be minimized if both address bytes are contained
in the first 3 bytes of a single 4-byte word. Such a loop should be manually located at an address
ending in 00b or the number of bytes in the loop should be increased (by padding with NOP
instructions) in order to minimize flash read current.
Rev. 0.5
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