C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 169
C8051F966-A-GQ
Manufacturer Part Number
C8051F966-A-GQ
Description
8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F966-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
32 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Available stocks
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C8051F966-A-GQ
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C8051F96x
13.2. Endianness
The CRC1 module is optimized to process big endian data. Data written to the CRC1IN SFR should be in
the normal bit order with the most significant bit stored in bit 7 and the least significant bit stored in bit 0.
The input data is shifted left into the CRC engine. The CRC1 module will process one byte at a time and
update the results for each byte. When used with the DMA, the first byte to be written should be stored in
the lowest address.
Some communications systems may transmit data least significant bit first and may require calculation of a
CRC in the transmission bit order. In this case, the bits must be flipped, using the CRC0FLIP SFR, before
writing to the CRC1IN SFR. The final 16-bit result may be flipped using the flip bit in the CRC1CN SFR.
Note that the polynomial is always written in big endian bit order.
Rev. 0.5
169
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