C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 309
C8051F966-A-GQ
Manufacturer Part Number
C8051F966-A-GQ
Description
8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F966-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
32 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F966-A-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F966-A-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
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Internal Register Definition 24.7. RTC0CF: SmaRTClock Configuration
SmaRTClock Address = 0x07
Name
Reset
Type
Bit
7
6
5
4
3
2
1
0
Bit
AUTORST Auto Reset Enable.
ALRM2EN Alarm 2 Enable.
ALRM1EN Alarm 1 Enable.
ALRM0EN Alarm 0 Enable.
Reserved Read = 0b; Must write 0b.
ALRM2
ALRM1
ALRM0
Name
R/W
7
0
Event Flag for Alarm 2.
This bit must be cleared by software. Writing a ‘1’ to this bit has no effect.
0: An Alarm 2 event has not occured since the last time the flag was cleared.
1: An Alarm 2 event has occured.
Event Flag for Alarm 1.
This bit must be cleared by software. Writing a ‘1’ to this bit has no effect.
0: An Alarm 1 event has not occured since the last time the flag was cleared.
1: An Alarm 1 event has occured.
Event Flag for Alarm 0.
This bit must be cleared by software. Writing a ‘1’ to this bit has no effect.
0: An Alarm 0 event has not occured since the last time the flag was cleared.
1: An Alarm 0 event has occured.
Enables the Auto Reset function to clear the counter when an Alarm 0 event occurs.
0: Auto Reset is disabled
1: Auto Reset is enabled.
0: Alarm 2 is disabled.
1: Alarm 2 is enabled.
0: Alarm 1 is disabled.
1: Alarm 1 is enabled.
0: Alarm 0 is disabled.
1: Alarm 0 is enabled.
ALRM2
R/W
6
0
ALRM1
R/W
5
0
ALRM0
R/W
Rev. 0.5
4
0
Function
AUTORST RTC2EN
R/W
3
0
R/W
2
0
C8051F96x
RTC1EN
R/W
1
0
RTC0EN
R/W
0
0
309
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