C8051F966-A-GQ Silicon Labs, C8051F966-A-GQ Datasheet - Page 177
C8051F966-A-GQ
Manufacturer Part Number
C8051F966-A-GQ
Description
8-bit Microcontrollers - MCU 32KB DC-DC LCD AES
Manufacturer
Silicon Labs
Datasheet
1.C8051F960-A-GQ.pdf
(492 pages)
Specifications of C8051F966-A-GQ
Rohs
yes
Core
8051
Processor Series
C8051
Data Bus Width
8 bit
Maximum Clock Frequency
24.5 MHz
Program Memory Size
32 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.8 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
QFP-80
Mounting Style
SMD/SMT
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14.1.1. AES Encryption/Decryption Core
The AES Encryption/Decryption Core is a digital implementation of the Advanced Encryption Standard
block cipher. The core may be used for either encryption or decryption. Encryption may be selected by set-
ting bit 5 in the AES0BCFG sfr. When configured for encryption, plaintext is written to the AES Core data
input and the encrypted ciphertext is read from the Data Output. Conversely, when configured for Decryp-
tion, encrypted ciphertext is written to the data input and decrypted plaintext is read form the Data Output.
When configured for Encryption, the encryption key must be written to the Key Input. When configured for
decryption, the decryption key must be written to the Key Input.
The AES core may also be used to generate a decryption key from a known encryption key. To generate a
decryption key, the core must be configured for encryption, the encryption key is written to the Key Input,
and the Decryption Key may be read from the Key output.
AES is a symmetric key encryption algorithm. This means that the decryption key may be generated from
an encryption key using a simple algorithm. Both keys must remain secret. If security of the encryption key
is compromised, one can easily generate the decryption key.
Since it is easy to generate the decryption key, only the encryption key may be stored in Flash memory.
14.1.2. Data SFRs
The data sfrs are used for the data flow into and out of the AES module. When used with the DMA, the
DMA itself will write to and read from the data sfrs. When used in manual mode, the data must be written to
the data sfrs one byte at a time in the proper sequence.
The AES0KIN sfr provides a data path for the AES core Key input. For an encryption operation, the
encryption key is written to the AES0KIN sfr, either by the DMA or direct sfr access. For a decryption oper-
ation, the decryption key must be written to the AES0KIN sfr.
The AES0BIN is the direct data input sfr for the AES block. For a simple encryption operation, the plaintext
is written to the AES0BIN sfr – either by the DMA or direct sfr access. For decryption, the ciphertext to be
decrypted is written to the AES0BIN sfr. The AES0BIN sfr is also used together with the AES0XIN when an
exclusive OR operation is required on the input data path.
The AES0XIN sfr provides an input data path to the exclusive OR operator. The AES0XIN is not used for
simple AES block cipher encryption or decryption. It is only use for block cipher modes that require an
exclusive OR operator on the input or output data.
The AES core requires that the input data bytes are written in a specific order. When used with the DMA,
this is managed by the internal state machine. When using direct sfr access, each of input data must be
written one byte at a time to each sfr in this particular order.
This sequence is repeated 16 times. When using a 192-bit or 256-bit key length, the remaining additional
key bytes are written after writing all sixteen of the AES0BIN and AES0XIN bytes.
After encryption or decryption is completed, the resulting data may be read from the AES0YOUT. Option-
ally, exclusive OR data may be written to the AES0XIN sfr before reading the AES0YOUT sfr.
1. Write AES0BIN
2. Write AES0XIN (optional)
3. Write AES0KIN
1. Write AES0XIN (optional)
2. Read AES0YOUT
Rev. 0.5
C8051F96x
177
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