AS4C8M16S-6TAN Alliance Memory, AS4C8M16S-6TAN Datasheet - Page 6

• Manufacturer Part Number: AS4C8M16S-6TAN
• Description: DRAM 128Mb, 3.3V, 166Mhz 8M x 16 SDRAM
• Manufacturer: Alliance Memory

Specifications of AS4C8M16S-6TAN

• Rohs: yes
• Data Bus Width: 16 bit
• Organization: 8 Mbit x 16
• Package / Case: TSOP-54
• Memory Size: 128 Mbit
• Maximum Clock Frequency: 143 MHz
• Access Time: 5.4 ns
• Supply Voltage - Max: 4.6 V
• Supply Voltage - Min: - 1 V
• Maximum Operating Current: 110 mA
• Maximum Operating Temperature: + 105 C
• Factory Pack Quantity: 108

Commands
1
2
3
4
FEBRUARY 2011
CLK
COMMAND
ADDRESS
BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address)
latching the row address on A0 to A11 at the time of this command, the selected row access is
initiated. The read or write operation in the same bank can occur after a time delay of t
from the time of bank activation. A subsequent BankActivate command to a different row in the same
bank can only be issued after the previous active row has been precharged (refer to the following
figure). The minimum time interval between successive BankActivate commands to the same bank
is defined by t
internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the two
banks. t
command is used, the Write command and the Block Write command perform the no mask write
operation.
BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9 and A11 = Don't care)
bank is switched from the active state to the idle state. This command can be asserted anytime after
t
bank can be active is specified by t
in any active bank within t
state and is ready to be activated again.
PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don‟t care, A10 = "H", A0-A9 and A11 = Don't care)
banks are not in the active state. All banks are then switched to the idle state.
Read command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A8 = Column Address)
row in an active bank. The bank must be active for at least t
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent data-
out element will be valid by the next positive clock edge (refer to the following figure). The DQs go
into high-impedance at the end of the burst unless other command is initiated. The burst length,
burst sequence, and CAS# latency are determined by the mode register, which is already
programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to
column 0 and continue).
RAS
Figure 3. BankActivate Command Cycle
(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
The BankActivate command activates the idle bank designated by the BA0, 1 signals.
The BankPrecharge command precharges the bank disignated by BA signal. The precharged
The PrechargeAll command precharges all banks simultaneously and can be issued even if all
The Read command is used to read a burst of data on consecutive clock cycles from an active
RRD
(min.) specifies the minimum time required between activating different banks. After this
RC
Bank A
Row Addr.
T0
Bank A
Activate
(min.). The SDRAM has four internal banks on the same chip and shares part of the
RAS# - CAS# delay(t
T1
NOP
RAS
(max.). At the end of precharge, the precharged bank is still in the idle
T2
NOP
RCD
RAS
)
(max.). Therefore, the precharge function must be performed
T3
R/W A with
AutoPrecharge
Bank A
Col Addr.
RAS# - Cycle time(t
6
(Burst Length = n, CAS# Latency = 3)
AutoPrecharge
RC
Tn+3
Bank B
Row Addr.
Bank B
Activate
RCD
)
Begin
RAS# - RAS# delay time(t
(min.) before the Read command is
Tn+4
NOP
Don’t Care
Tn+5
NOP
RRD
)
AS4C8M16S
Bank A
Row Addr.
Tn+6
Bank A
Activate
RCD
(min.)
By