as4c8m16s Alliance Memory, Inc, as4c8m16s Datasheet

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as4c8m16s

Manufacturer Part Number
as4c8m16s
Description
128mb/ 8m X 16 Bit Synchronous Dram Sdram
Manufacturer
Alliance Memory, Inc
Datasheet

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Part Number:
as4c8m16s-7TCN
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Alliance Memory Confidential
Features
• Fast access time from clock: 5/5.4 ns
• Fast clock rate: 166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• 2M word x 16-bit x 4-bank
• Programmable Mode registers
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• CKE power down mode
• Single +3.3V ± 0.3V power supply
• Interface: LVTTL
• 54-pin 400 mil plastic TSOP II package
Overview
The AS4C8M16S SDRAM is a high-speed CMOS
synchronous DRAM containing 128 Mbits. It is
internally configured as 4 Banks of 2M word x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with
the registration of a BankActivate command which
is then followed by a Read or Write command.
Read or Write burst lengths of 1, 2, 4, 8, or full page,
with a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh are easy to use.
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth and particularly well suited to high
performance PC applications.
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
- Pb free and Halogen free
The AS4C8M16S provides for programmable
FEBRUARY 2011
By having a programmable mode register, the
128Mb/ 8M x 16 bit Synchronous DRAM (SDRAM)
Table1. Key Specifications
tCK3 Clock Cycle time(min.)
tAC3 Access time from CLK(max.)
tRAS Row Active time(min.)
tRC Row Cycle time(min.)
Table 2. Ordering Information
T: indicates TSOPII Package,
N: indicates Pb and Halogen Free for TSOPII Package
Figure 1. Pin Assignment (Top View)
A10/AP
1
AS4C8M16S -6TCN
AS4C8M16S -7TCN
VDDQ
LDQM
VDDQ
VSSQ
VSSQ
CAS#
RAS#
WE#
VDD
VDD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
BA1
VDD
BA0
CS#
Part Number
A0
A2
A1
A3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
2
3
4
5
6
7
8
9
AS4C8M16S
Frequency
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
166MHz
143MHz
VSS
DQ9
VSS
NC/RFU
UDQM
CLK
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
VDDQ
DQ8
CKE
NC
A11
A8
A7
A6
A5
A4
VSS
A9
AS4C8M16S
Package
TSOP II
TSOP II
- 6/7
42/42 ns
60/63 ns
6/7
5/5.4 ns
ns

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