MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 215

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 148: Deep Power-Down Mode
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
CKE
CK#
CK
All banks idle with no
activity on the data bus
1
Notes:
NOP
T0
1. Clock must be stable prior to CKE going HIGH.
2. DPD = deep power-down.
3. Upon exit of deep power-down mode, a full DRAM initialization sequence is required.
t
IS
DPD
T1
Enter deep power-down mode
2
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
T2
(
(
(
(
)
(
)
t
)
)
)
(
CKE
(
(
(
)
(
)
)
)
)
215
Ta0
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
NOP
Ta1
Exit deep power-down mode
T = 200µs
© 2009 Micron Technology, Inc. All rights reserved.
Ta2
NOP
Power-Down
Don’t Care
Ta3
PRE
3