MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 159

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 E IT
• Manufacturer: Micron

Figure 106: READ Command
WRITE
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Note:
BA0, BA1
The WRITE command is used to initiate a burst write access to an active row. The val-
ues on the BA0 and BA1 inputs select the bank; the address provided on inputs A[I:0]
(where I = the most significant column address bit for each configuration) selects the
starting column location. The value on input A10 determines whether auto precharge is
used. If auto precharge is selected, the row being accessed will be precharged at the end
of the WRITE burst; if auto precharge is not selected, the row will remain open for subse-
quent accesses. Input data appearing on the DQ is written to the memory array, subject
to the DM input logic level appearing coincident with the data. If a given DM signal is
registered LOW, the corresponding data will be written to memory; if the DM signal is
registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not
be executed to that byte/column location.
If a WRITE or a READ is in progress, the entire data burst must be complete prior to
stopping the clock (see Clock Change Frequency (page 216)). A burst completion for
WRITEs is defined when the write postamble and
Address
1. EN AP = enable auto precharge; DIS AP = disable auto precharge.
CAS#
RAS#
WE#
A10
CK#
CKE
CS#
CK
HIGH
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Column
EN AP
DIS AP
Bank
Don’t Care
159
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t
WR or
t
WTR are satisfied.
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Commands