MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 132

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MT29C4G48MAZAPAKD-5 E IT

Manufacturer Part Number
MT29C4G48MAZAPAKD-5 E IT
Description
Manufacturer
Micron
Datasheet
Figure 98: INTERNAL DATA MOVE
Figure 99: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
WE#
I/O[7:0]
RDY
I/Ox
CE#
ALE
RE#
CLE
R/B#
00h
t
WC
00h
Source address
add 1
(5 cycles)
Col
Address
add 2
Col
35h
add 1
Row
t
R_ECC
add 2
Row
SR bit 0 = 0 READ successful
SR bit 1 = 0 READ error
add 3
Row
70h
(or 30h)
35h
Status
t
WB
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Busy
t R
00h
85h
132
add 1
Col
D
Asynchronous Interface Timing Diagrams
D
OUT
OUT
add 2
Col
is optional
add 1
Row
Micron Technology, Inc. reserves the right to change products or specifications without notice.
add 2
Row
85h
Destination address
add 3
Row
(5 cycles)
Address
t
ADL
Data
1
Data Input
Optional
10h
t
Data
PROG_ECC
N
© 2009 Micron Technology, Inc. All rights reserved.
10h
t
WB
SR bit 0 = 0 READ successful
SR bit 1 = 0 READ error
70h
t
PROG
Busy
READ STATUS
command
Status
70h
t
WHR
Don’t Care
00h
Status

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