MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 103

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MT29C4G48MAZAPAKD-5 E IT

Manufacturer Part Number
MT29C4G48MAZAPAKD-5 E IT
Description
Manufacturer
Micron
Datasheet
Figure 74: TWO-PLANE PROGRAM PAGE with RANDOM DATA INPUT
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
R/B#
R/B#
I/Ox
I/Ox
80h
1
85h
Address (5 cycles)
1st-plane address
Unlimited number of repetitions
address than previous
5 address cycles, for
Different column
Address (2 cycles)
2nd plane only
Data
Data
input
input
85h
address than previous
Unlimited number of repetitions
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
5 address cycles, for
10h
Different column
Address (2 cycles)
1st plane only
t PROG
103
Data
input
Micron Technology, Inc. reserves the right to change products or specifications without notice.
11h
t DBSY
80h
2nd-plane address
Address (5 cycles)
Two-Plane Operations
© 2009 Micron Technology, Inc. All rights reserved.
Data
input
1

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