MT29C4G48MAZAPAKD-5 E IT Micron, MT29C4G48MAZAPAKD-5 E IT Datasheet - Page 102
MT29C4G48MAZAPAKD-5 E IT
Manufacturer Part Number
MT29C4G48MAZAPAKD-5 E IT
Description
Manufacturer
Micron
Datasheet
1.MT29C4G48MAZAPAKD-5_IT.pdf
(218 pages)
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Figure 72: TWO-PLANE PAGE READ with RANDOM DATA READ
Figure 73: TWO-PLANE PROGRAM PAGE
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
R/B#
R/B#
R/B#
I/Ox
I/Ox
I/Ox
RE#
RE#
1
00h
80h
06h
Address (5 cycles)
Plane 0 address
1st-plane address
Address (5 cycles)
Address (5 cycles)
Plane 1 address
00h
Data
E0h
Address (5 cycles)
Plane 1 address
input
11h
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Plane 1 data
t DBSY
30h
Data output
80h
t R
102
2nd-plane address
05h
Address (5 cycles)
Plane 0 data
Data output
(2 cycles)
Address
Micron Technology, Inc. reserves the right to change products or specifications without notice.
E0h
Data
05h
(2 cycles)
Address
Plane 1 data
input
Data output
10h
E0h
Two-Plane Operations
t PROG
© 2009 Micron Technology, Inc. All rights reserved.
Plane 0 data
70h
Data output
Status
1
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