DM9010BI DAVICOM [Davicom Semiconductor, Inc.], DM9010BI Datasheet - Page 20

• Manufacturer Part Number: DM9010BI
• Description: Industrial-temperature 10/100 Mbps Single Chip Ethernet Controller With General Processor Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.12 EEPROM & PHY Control Register (0BH)
6.13 EEPROM & PHY Address Register (0CH)
6.14 EEPROM & PHY Data Register (EE_PHY_L：0DH
6.15 Wake up Control Register (0FH)
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Bit
7:6
7:0
7:0
Bit
7:6
7:6
5:0
Bit
Bit
5
4
3
4
3
2
1
0
5
4
3
2
1
0
RESERVED
SAMPLEEN
RESERVED
EE_PHY_H
EE_PHY_L
MAGICEN
PHY_ADR
LINKEN
ERPRW
RXPCS
ERPRR
Name
EROA
Name
Name
BKPM
BKPA
RXPS
EPOS
ERRE
FLCE
Name
REEP
WEP
PH01,RW
HPS0,RW
HPS0,RW
HPS0,R/C
HPS0,RW
PH0,RW
HPS0,RO
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RW
PH0,RO
Default
Default
Default
P0,RW
P0,RW
P0,RW
0,RO
Type
0,RO
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
Reserved
Reload EEPROM. Driver needs to clear it up after the operation completes
Write EEPROM Enable
EEPROM or PHY Operation Select
When reset, select EEPROM; when set, select PHY
EEPROM Read or PHY Register Read Command. Driver needs to clear it up after
the operation completes.
EEPROM Write or PHY Register Write Command. Driver needs to clear it up after
the operation completes.
EEPROM Access Status or PHY Access Status
When set, it indicates that the EEPROM or PHY access is in progress
PHY Address bit 1 and 0; the PHY address bit [4:2] is force to 0. Force to 01 if
internal PHY is selected
EEPROM Word Address or PHY Register Address
EEPROM or PHY Low Byte Data
This data is made to write low byte of word address defined in Reg. CH to
EEPROM or PHY
EEPROM or PHY High Byte Data
This data is made to write high byte of word address defined in Reg. CH to
EEPROM or PHY
Reserved
When set, it enables Link Status Change Wake up Event
This bit will not be affected after software reset
When set, it enables Sample Frame Wake up Event
This bit will not be affected after software reset
When set, it enables Magic Packet Wake up Event
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when any
packet comes and RX SRAM is over BPHW
Back Pressure Mode
This mode is for half duplex mode only. It generates a jam pattern when a packet’s
DA matches and RX SRAM is over BPHW
RX Pause Packet Status, latch and read clearly
RX Pause Packet Current Status
Flow Control Enable
Set to enable the flow control mode (i.e. to disable TX function)
EE_PHY_H：0EH)
Description
Description
Description
Description
DM9010BI
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