DM9161BIEP DAVICOM [Davicom Semiconductor, Inc.], DM9161BIEP Datasheet
DM9161BIEP
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DM9161BIEP Summary of contents
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DAVICOM Semiconductor, Inc. Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver 1 DM9161BI DATA SHEET Preliminary Version: DM9161BI-DS-P01 July 16, 2008 Preliminary Version: DM9161BI-DS-P01 July 16, 2008 ...
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Table of Contents 1. General Description...................................................................3 2. Features ....................................................................................3 3. Block Diagram ...........................................................................4 4. Pin Configuration: ......................................................................5 5. Pin Description ..........................................................................6 5.1 Normal MII Interface, 21 pins ..................................................6 5.2 Media Interface, 4 pins ............................................................8 5.3 LED Interface, 3 pins ...............................................................8 ...
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General Description The DM9161BI is a Industrial-grade physical layer, single-chip, and low power 100BASE-TX and 10BASE-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, ...
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Block Diagram Preliminary Version: DM9161BI-12-DS-P01 July 16, 2008 Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver DM9161BI 4 ...
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Pin Configuration: 5 Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver DM9161BI Preliminary Version: DM9161BI-12-DS-P01 July 16, 2008 ...
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Pin Description I: Input, O: Output, LI: Latch input when power-up/reset, Z: Tri-State output, U: Pulled high D: Pulled low 5.1 Normal MII Interface, 21 pins Pin No. Pin Name 16 TXER/TXD [4] 20,19,18,17 TXD [0:3] 21 TXEN 22 ...
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RXCLK /10BTSER 35 CRS /PHYAD[4] 36 COL /RMII 37 RXDV /TESTMODE 38 RXER/RXD[4] /RPTR 31 LEDMODE 40 RESET# 7 Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver O, Receive Clock Z, The received clock provides the timing ...
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Media Interface, 4 pins Pin No. Pin Name 3,4 RX+ RX- 7,8 TX+ TX- 5.3 LED Interface, 3 pins Pin No. Pin Name 11 LED0 /OP0 12 LED1 /OP1 13 LED2 /OP2 5.4 Mode, 3 pins Pin No. Pin ...
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Bias and Clock, 4 pins Pin No. Pin Name 47 BGRESG 48 BGRES 42 XT2 43 XT1 *RMII mode REF_CLK 50MHz choice XT1 or XT2. 5.6 Power, 12 pins Pin No. Pin Name 1,2 AVDDR 9 AVDDT 5 AGND ...
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Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI (7-Wired) Mode Pin No. Normal MII Mode 20,19 TXD [0:1] 18,17 TXD [2:3] 21 TXEN 16 TXER/TXD [4] 22 TXCLK 29,28 RXD [0:1] 27,26 RXD[2:3] 38 RXER/RXD[4]/RPTR/NODE RPTR/NODE 37 ...
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LED Configuration LEDs flash once per 500ms after power-on reset or software reset by writing PHY register. All LED pins are dual function pins, which can be configured as either active high or low by pulling them low or ...
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LED Function Description Normal LED mode Name Pin LED0 11 LED1 12 SPEED: 100M CABLESTS / LINKSTS Name Pin LED2 13 CABLESTS Without Cable 14 / LINKSTS connection * Pin 31 = LEDMODE For Dual-LED. Name Pin Link Fail ...
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Functional Description The DM9161BI Fast Ethernet single chip transceiver, providing the functionality as specified in IEEE 802.3u, integrates a complete 100Base-TX module and a complete 10Base-T module. The DM9161BI provides a Media Independent Interface (MII) as defined in the ...
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MII Interface (continued) • TXER (transmit coding synchronously with respect to TXCLK. If TXER is asserted for one or more clock periods, and TXEN is asserted, the PHY will emit one or more symbols that are not part of the ...
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Operation The 100Base-TX transmitter receives 4-bit nibble data clocked in at 25MHz at the MII, and outputs a scrambled 5-bit encoded MLT-3 signal to the media at 100Mbps. The on-chip clock circuit converts the 25MHz clock into a ...
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The block diagram in figure 7-3 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter - NRZ to NRZI ...
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Code Group Symbol Industrial-grade 10/100 ...
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D Binary In 7.2.2 100Base-TX Receiver The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data, which is then provided to the MII. The receive section contains the following functional blocks: ...
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The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125MHz reference clock. The extracted and synchronized clock and data are presented to the NRZI ...
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Auto-Negotiation (continued) Auto-negotiation also provides a parallel detection function for devices that do not support the Auto-negotiation feature. During Parallel detection there is no exchange of configuration information, instead, the receive signal is examined discovered that the ...
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Power Reduced Mode The Signal detect circuit is always turned on to monitor whether there is any signal on the media. In case of cable disconnection, DM9161BI will automatically turn off the power and enter the Power Reduced mode, ...
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MII Register Description AD Name CONTROL Reset Loop Speed Auto-N back select Enable STATUS T4 TX FDX TX HDX 10 FDX Cap. Cap. Cap. Cap ...
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Basic Mode Control Register (BMCR Bit Bit Name 0.15 Reset 0.14 Loopback 0.13 Speed selection 0.12 Auto-negotiation enable 0.11 Power down 0.10 Isolate 0.9 Restart Auto-negotiation 23 Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver ...
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Duplex mode 0.7 Collision test 0.6-0.0 Reserved 8.2 Basic Mode Status Register (BMSR Bit Bit Name 1.15 100BASE-T4 1.14 100BASE-TX full-duplex 1.13 100BASE-TX half-duplex 1.12 10BASE-T full-duplex 1.11 10BASE-T half-duplex 1.10-1.7 Reserved 1.6 MF preamble suppression 1.5 ...
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Jabber detect 1.0 Extended capability 8.3 PHY ID Identifier Register #1 (PHYID1 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9161BI. The Identifier consists of a concatenation of the Organizationally ...
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Auto-negotiation Advertisement Register (ANAR This register contains the advertised abilities of this DM9161BI device as they will be transmitted to its link partner during Auto-negotiation. Bit Bit Name 4.15 NP 4.14 ACK 4.13 RF 4.12-4.11 Reserved 4.10 ...
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Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit Bit Name 5.15 NP 5.14 ACK 5.13 RF 5.12-5.11 Reserved 5.10 FCS 5.9 T4 5.8 TX_FDX ...
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Auto-negotiation Expansion Register (ANER Bit Bit Name 6.15-6.5 Reserved 6.4 PDF 6.3 LP_NP_ABLE 6.2 NP_ABLE 6.1 PAGE_RX 6.0 LP_AN_ABLE 8.8 DAVICOM Specified Configuration Register (DSCR Bit Bit Name 16.15 BP_4B5B 16.14 BP_SCR 16.13 BP_ALIGN 16.12 ...
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F_LINK_100 16.6 SPLED_CTL 16.5 COLLED_CTL 16.4 RPDCTR-EN 16.3 SMRST 16.2 MFPSC 16.1 SLEEP 16.0 RLOUT 29 Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver latched into this bit at power-up/reset 0 = Normal MII 1 = Enable ...
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DAVICOM Specified Configuration and Status Register (DSCSR Bit Bit Name Default 17.15 100FDX 1, RO 17.14 100HDX 1, RO 17.13 10FDX 1, RO 17.12 10HDX 1, RO 17.11-17. Reserved 17.8-17.4 PHYADR[4 (PHYADR), :0] RW ...
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Configuration/Status (10BTCSR Bit Bit Name Default 18.15 Reserved 0, RO 18.14 LP_EN 1, RW 18.13 HBE 1,RW 18.12 SQUELCH 1, RW 18.11 JABEN 1, RW 18.10 10BT_SER 34),RW 18.9-18.1 Reserved 0, RO 18.0 POLR 0, RO ...
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Register – 20 Bit Bit Name 20.15 TSTSE1 20.14 TSTSE2 20.13 FORCE_TXSD 20.12 TSTSEL3 20.11 PREAMBLEX 20.10 TX10M_PWR 20.9 NWAY_PWR 20.8 Reserved 20.7 MDIX_CNTL MDI/MDIX,RO The polarity of MDI/MDIX value 20.6 AutoNeg_dpbk 20.5 Mdix_fix Value 20.4 Mdix_do ...
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Reserved 12 21.11 FDX mask 21.10 SPD mask 21.12 LINK mask 21.8 INTR mask 21.7-21.5 Reserved 21.4 FDX change 21.3 SPD change 21.2 LINK change 21.1 Reserved 21.0 INTR status 8.14 DAVICOM Specified Receive Error Counter Register (RECR) – ...
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DAVICOM Hardware Reset Latch State Register (RLSR) – 24 Bit Bit Name 24.15 LH_LEDMODE 24.14 LH_MDINTR 24.13 LH_CSTS 24.12 LH_ISO 24.11 LH_RMII 24.10 LH_TP10SER 24.9 LH_REPTR 24.8 LH_TSTMOD 24.7 LH_OP2 24.6 LH_OP1 24.5 LH_OP0 24.4 LH_PH4 24.3 LH_PH3 24.2 ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DM9161BI Max. Unit Conditions 3.6 V 5.5 V 3.6 V +150 °C +260 °C DM9161BIEP Typ. Max. Unit Conditions 3.300 3.465 V °C - +85 130 - m A 168(61 ...
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DC Electrical Characteristics (DVDD = 3.3V) Symbol Parameter TTL Inputs (TXD0~TXD3, TXCLK, MDC, MDIO, TXEN, TXER, RXEN, TESTMODE, RMII, PHYAD0~4, OPMODE0-2, RPTR, RESET Input Low Voltage IL V Input High Voltage IH I Input Low Leakage Current ...
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Power On Reset Timing RESET# Strap pins Symbol Parameter T1 RESET# Low Period T2 Strap pin hold time with RESET# 9.4.4 MDC/MDIO Timing Symbol Parameter t MDC Cycle Time 0 t1 MDIO Setup Before MDC t2 MDIO Hold After ...
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Transmit Timing Parameters Symbol Parameter t TXCLK Cycle Time TXc TXCLK High/Low Time TXh TXl t TXD [0:3], TXEN, TXER Setup To TXCLK High TXD [0:3], TXEN, TXER Hold From TXCLK High ...
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MII 100BASE-TX Receive Timing Diagram RXCLK RXD [0:3], RXDV, RXER CRS RX+/- COL 9.4.11 MII 10BASE-T Nibble Transmit Timing Parameters Symbol t TXD[0:3), TXEN, TXER Setup To TXCLK High TXD[0:3], TXEN, TXER Hold From TXCLK High ...
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MII 10BASE-T Receive Nibble Timing Parameters Symbol t RXD [0:3], RXDV, RXER Setup To RXCLK High RXD [0:3], RXDV, RXER Hold From RXCLK High RX+/- To RXD [0:3] Out (Rx Latency ...
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Auto-negotiation and Fast Link Pulse Timing Diagram Clock Pulse FAST LINK PULSES FLP Burst FLP Bursts 9.4.17 RMII Receive Timing Diagram 9.4.18 RMII Transmit Timing Diagram 41 Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver Data Pulse ...
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RMII Timing Diagram REF_CLK TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER 9.4.20 RMII Timing Parameter Symbol Parameter Fref REF_CLK Frequency Tref% REF_CLK Duty Cycle Tref REF_CLK Clock Cycle Tsu TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RX_ER Data Setup to REF_CLK rising edge Thold ...
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Magnetic Specification Requirements Refer to the following table for 10/100M magnetic specification requirements. The magnetic which meet these requirements are available from a variety of magnetic manufacturers. Designers should test and Parameter turns ratio Inductance Insertion ...
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Package Information LQFP 48L (F.P. 2mm) Outline Dimensions Symbol Dimensions in inches Min. Nom. Max 0.063 A1 0.002 - 0.006 A2 0.053 0.055 0.057 b 0.007 0.009 0.011 b1 0.007 0.008 0.009 C 0.004 - 0.008 ...
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... Order Information Part Number Pin Count DM9161BIEP 48 Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits Semiconductor are covered by the warranty and patent indemnification, and the provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description, regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement ...