DM9010BI DAVICOM [Davicom Semiconductor, Inc.], DM9010BI Datasheet - Page 16

• Manufacturer Part Number: DM9010BI
• Description: Industrial-temperature 10/100 Mbps Single Chip Ethernet Controller With General Processor Interface
• Manufacturer: DAVICOM [Davicom Semiconductor, Inc.]

6.1 Network Control Register (00H)
6.2 Network Status Register (01H)
6.3 TX Control Register (02H)
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
2:1
Bit
Bit
Bit
7
6
5
4
3
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
RESERVED
RESERVED
RESERVED
RESERVED
CRC_DIS2
CRC_DIS1
PAD_DIS2
PAD_DIS1
EXT_PHY
WAKEEN
WAKEST
EXCECM
TX2END
TX1END
SPEED
LINKST
TXREQ
RXOV
Name
Name
TJDIS
Name
FCOL
FDX
RST
LBK
PHS0,RO RX FIFO Overflow
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PHS0,RW
PH0,RW
PH0,RW
Default
RW/C1
RW/C1
RW/C1
PHS00,
Default
Default
PHS0,
PHS0,
P0,RW
X,RO
X,RO
0,RO
0,RO
0,RO
0,RO
P0,
RW
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
Media Speed 0:100Mbps 1:10Mbps, when Internal PHY is used. This bit has no
meaning when LINKST=0
Link Status 0:link failed 1:link OK, when Internal PHY is used
Wakeup Event Status. Clears by read or write 1
This bit will not be affected after software reset
Reserved
TX Packet 2 Complete Status. Clears by read or write 1
Transmit completion of packet index 2
TX Packet 1 Complete status. Clears by read or write 1
Transmit completion of packet index 1
Reserved
Selects external PHY when set. Selects Internal PHY when clear. This bit will not
be affected after software reset
Wakeup Event Enable
When set, it enables the wakeup function. Clearing this bit will also clears all
wakeup event status
This bit will not be affected after a software reset
Reserved
Force Collision Mode, used for testing
Full-Duplex Mode. Read only on Internal PHY mode. R/W on External PHY mode
Loopback Mode
Bit
Software reset and auto clear after 10us
Reserved
Transmit Jabber Disable
When set, the transmit Jabber Timer (2048 bytes) is disabled. Otherwise it is Enable
Excessive Collision Mode Control : 0:aborts this packet when excessive collision
counts more than 15, 1: still tries to transmit this packet
PAD Appends Disable for Packet Index 2
CRC Appends Disable for Packet Index 2
PAD Appends Disable for Packet Index 1
CRC Appends Disable for Packet Index 1
TX Request. Auto clears after sending completely
0
0
1
1
2 1
0
1
0
1
Normal
MAC Internal Loopback
(Reserved)
Internal PHY 100M mode digital Loopback
Description
Description
Description
DM9010BI
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