DM9000BEP DAVICOM [Davicom Semiconductor, Inc.], DM9000BEP Datasheet
DM9000BEP
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DM9000BEP Summary of contents
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DAVICOM Semiconductor, Inc. With General Processor Interface Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface DM9000B Ethernet Controller DATA SHEET DM9000B Final Version: DM9000B-DS-F02 June 4, 2009 1 ...
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General Description........................................................................................................... 6 2. Block Diagram.................................................................................................................... 6 3. Features.............................................................................................................................. 7 4. Pin Configuration............................................................................................................... 8 4.1 (16-bit mode) ................................................................................................................................................. 8 4.2 (8-bit mode) ................................................................................................................................................... 9 5. Pin Description ................................................................................................................ 10 5.1 Processor Interface ..................................................................................................................................... 10 5.1.1 8-bit mode pins......................................................................................................................................... 10 ...
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Wake Up Control Register ( 0FH ) (in 8-bit mode).................................................................................... 19 6.16 Physical Address Register ( 10H~15H ) ................................................................................................... 19 6.17 Multicast Address Register ( 16H~1DH ) .................................................................................................. 19 6.18 General purpose control Register ( 1EH ) ( For ...
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Basic Mode Control Register (BMCR ................................................................................................. 28 8.2 Basic Mode Status Register (BMSR) - 01................................................................................................... 29 8.3 PHY ID Identifier Register #1 (PHYID1 .............................................................................................. 30 8.4 PHY ID Identifier Register #2 (PHYID2 .............................................................................................. ...
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Power down Mode ............................................................................................................................. 43 9.11.2 Reduced Transmit Power Mode......................................................................................................... 43 10. DC and AC Electrical Characteristics .......................................................................... 44 10.1 Absolute Maximum Ratings ( 25 10.1.1 Operating Conditions ......................................................................................................................... 44 10.2 DC Electrical Characteristics (VDD = 3.3V).............................................................................................. 44 10.3 ...
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General Description The DM9000B is a fully integrated and cost-effective low pin count single chip Fast Ethernet controller with a general processor interface, a 10/100M PHY and 4K Dword SRAM designed with low power and high performance ...
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Features ■ Supports processor interface: byte/word of I/O command to internal memory data operation ■ Integrated 10/100M transceiver With HP Auto-MDIX ■ Supports back pressure mode for half-duplex ■ IEEE802.3x flow control for full-duplex mode ■ Supports wakeup frame, ...
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Pin Configuration 4.1 (16-bit mode) CS# LED2 LED1 PWRST# TEST VDD X2 X1 GND SD RXGND BGGND Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface DM9000B 42 (16-bit mode) 43 ...
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CS# LED2 LED1 PWRST# TEST VDD X2 X1 GND SD RXGND BGGND Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface DM9000B 42 (8-bit mode ...
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Pin Description I = Input O = Output # = asserted low 5.1 Processor Interface Pin No. Pin Name 35 IOR# 36 IOW# 37 CS# 32 CMD 34 INT O,PD 18,17,16, 14,13,12, SD0~7 I/O,PD 11,10 31,29,28, 27,26,25, SD8~15 I/O,PD ...
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GP3,GP2,GP1 5.2 EEPROM Interface Pin No. Pin Name I/O,PD IO Data to EEPROM 19 EEDIO 20 EECK O,PD 21 EECS O,PD 5.3 Clock Interface Pin No. Pin Name 5.4 LED Interface Pin No. Pin Name ...
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RX+,RX- 5,47 RXGND 6 TXGND 7,8 TX+,TX- 5.6 Miscellaneous Pin No. Pin Name 41 TEST 40 PWRST# 5.7 Power Pins Pin No. Pin Name 23,30,42 VDD 15,33,45 GND 5.8 strap pins table 1: pull-high 1K~10K, 0: floating (default) Pin ...
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Vendor Control and Status Register Set The DM9000B implements several control and status registers, which can be accessed by the host. These CSRs Register NCR Network Control Register NSR Network Status Register TCR TX Control Register TSR I TX ...
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RSCCR Resume System Clock Control Register MRCMDX Memory Data Pre-Fetch Read Command Without Address Increment Register MRCMDX1 Memory Data Read Command With Address Increment Register MRCMD Memory Data Read Command With Address Increment Register MRRL Memory Data Read_ address Register ...
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Network Status Register (01H) Bit Name Default 7 SPEED X,RO 6 LINKST X,RO P0, 5 WAKEST RW/C1 4 RESERVED 0,RO PS0, 3 TX2END RW/C1 PS0, 2 TX1END RW/C1 1 RXOV PS0,RO 0 RESERVED 0,RO 6.3 TX Control Register (02H) ...
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TX Status Register II ( 04H ) for packet index I I Bit Name Default 7 TJTO PS0, PS0, PS0, PS0,RO 3 COL PS0, PS0,RO 1:0 RESERVED 0,RO 6.6 RX Control ...
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Receive Overflow Counter Register ( 07H ) Bit Name Default 7 RXFU PS0,R/C 6:0 ROC PS0,R/C 6.9 Back Pressure Threshold Register (08H) Bit Name Default 7:4 BPHW PS3, RW 3:0 JPT PS7, RW 6.10 Flow Control Threshold Register ( ...
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RX/TX Flow Control Register ( 0AH ) Bit Name Default 7 TXP0 PS0,RW 6 TXPF PS0,RW 5 TXPEN PS0,RW 4 BKPA PS0,RW 3 BKPM PS0,RW 2 RXPS PS0,R/C 1 RXPCS PS0,RO 0 FLCE PS0,RW 6.12 EEPROM & PHY Control ...
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Wake Up Control Register ( 0FH ) (in 8-bit mode) Bit Name Type 7:6 RESERVED 0,RO 5 LINKEN P0,RW 4 SAMPLEEN P0,RW 3 MAGICEN P0,RW 2 LINKST P0,RO 1 SAMPLEST P0,RO 0 MAGICST P0,RO 6.16 Physical Address Register ( ...
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General purpose Register ( 1FH ) ( For 8 Bit mode only, for 16 bit mode, see reg . 34H) Bit Name Default 7 RESERVED 0,RO 6-4 GPO P0,RW P0,RW 3:1 GPIO 0 PHYPD ET1,WO 6.20 TX SRAM Read ...
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RLCP P0,RW 5 DTU P0,RW 4 ONEPM P0,RW 3~0 IFGS P0,RW 6.26 Operation Test Control Register ( 2EH ) Bit Name Default 7~6 SCC P0,RW 5 RESERVED P0,RW 4 SOE P0,RW 3 SCS P0,RW 2~0 PHYOP P0,RW 6.27 Special ...
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Early Transmit Control/Status Register ( 30H ) Bit Name Default 7 ETE PS0 ETS2 PS0,RO 5 ETS1 PS0,RO 4~2 RESERVED 000,RO 1~0 ETT PS0,RW 6.29 Check Sum Control Register ( 31H ) Bit Name Default 7~3 RESERVED ...
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MII PHY Address Register ( 33H ) Bit Name Default 7 ADR_EN HPS0,R W 6~5 Reserved HPS0,RO Reserved 4~0 EPHYADR HPS01,R W 6.32 LED Pin Control Register ( 34H ) Bit Name Default 7:2 Reserved PS0,RO 1 GPIO P0,RW ...
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INT Pin Control Register ( 39H ) Bit Name Default 7:2 Reserved PS0,RO 1 INT_TYPE PET0,RW 0 INT_POL PET0,RW 6.35 System Clock Turn ON Control Register ( 50H ) Bit Name Default 7:1 Reserved - 0 DIS_CLK P0,W 6.36 ...
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Memory data write command with address increment Register (F8H) Bit Name Default 7:0 MWCMD X,WO 6.43 Memory data write address Register (FAH~FBH) Bit Name Default 7:0 MDWAH PS0,RW 7:0 MDWAL PS0,RW 6.44 TX Packet Length Register (FCH~FDH) Bit Name ...
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EEPROM Format name Word MAC address 0 Auto Load Control 3 Vendor ID 4 Product ID 5 Pin control 6 Wake-up mode control 7 Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface offset 0~5 6 ...
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PHY Register Description ADD Name CONTR Reset Loop Speed Auto-N OL back select Enable STATUS T4 TX FDX TX HDX 10 FDX Cap. Cap. Cap. Cap ...
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Basic Mode Control Register (BMCR Bit Bit Name 0.15 Reset 0.14 Loop-back 0.13 Speed selection 0.12 Auto-negotiation enable 0.11 Power down 0.10 Isolate 0.9 Restart Auto-negotiation 0.8 Duplex mode 0.7 Collision test 0.6-0.0 Reserved Final Version: DM9000B-13-DS-F02 ...
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Basic Mode Status Register (BMSR Bit Bit Name 1.15 100BASE-T4 1.14 100BASE-TX full-duplex 1.13 100BASE-TX half-duplex 1.12 10BASE-T full-duplex 1.11 10BASE-T half-duplex 1.10-1.7 Reserved 1.6 MF preamble suppression 1.5 Auto-negotiation Complete 1.4 Remote fault 1.3 Auto-negotiation ability ...
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Jabber detect 1.0 Extended capability 8.3 PHY ID Identifier Register #1 (PHYID1 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9000B. The Identifier consists of a concatenation of the Organizationally ...
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Auto-negotiation Advertisement Register (ANAR This register contains the advertised abilities of this DM9000B device as they will be transmitted to its link partner during Auto-negotiation. Bit Bit Name 4.15 NP 4.14 ACK 4.13 RF 4.12 Reserved -4.11 ...
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Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit Bit Name 5.15 NP 5.14 ACK 5.13 RF 5.12 Reserved -5.11 5.10 FCS 5.9 T4 5.8 ...
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NP_ABLE 6.1 PAGE_RX 6.0 LP_AN_ABLE 8.8 DAVICOM Specified Configuration Register (DSCR Bit Bit Name 16.15 BP_4B5B 16.14 BP_SCR 16.13 BP_ALIGN 16.12 BP_ADPOK 16.11 Reserved 16.10 TX/FX 16.9 Reserved 16.8 Reserved 16.7 F_LINK_100 16.6 SPLED_CTL 16.5 COLLED_CTL 16.4 ...
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SMRST 16.2 MFPSC 16.1 SLEEP 16.0 RLOUT 8.9 DAVICOM Specified Configuration and Status Register (DSCSR Bit Bit Name Default 17.15 100FDX 1, RO 17.14 100HDX 1, RO 17.13 10FDX 1, RO 17.12 10HDX 1, RO 17.11 Reserved ...
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PHYADR[4 (PHYADR), -17.4 :0] RW 17.3 ANMB[3: -17.0 8.10 10BASE-T Configuration/Status (10BTCSR Bit Bit Name Default 18.15 Reserved 0, RO 18.14 LP_EN 1, RW 18.13 HBE 1,RW 18.12 SQUELCH 1, RW 18.11 JABEN 1, ...
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Power down Control Register (PWDOR Bit Bit Name Default 19.15 Reserved 0, RO -19.9 19.8 PD10DRV 0, RW 19.7 PD100DL 0, RW 19.6 PDchip 0, RW 19.5 PDcom 0, RW 19.4 PDaeq 0, RW 19.3 PDdrv 0, ...
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Mdix_down 20.3 MonSel1 20.2 MonSel0 20.1 Reserved 20.0 PD_value 8.13 DSP Control Register (PSCR) – 27 Bit Bit Name 27.15-0 DSP 8.14 Power Saving Control Register (PSCR) – 29 Bit Bit Name 29.15-12 RESERVED 29.11 PREAMBLEX 29.10 AMPLITUDE 29.9 ...
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Functional Description 9.1 Host Interface The host interface is a general processor local bus that using chip select (pin CS#) to access DM9000B. Pin CS# is default low active which can be re-defined by EEPROM setting. There are only ...
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Operation The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter - NRZ to NRZI Converter - NRZI to MLT-3 - MLT-3 Driver 9.5.1 4B5B Encoder The 4B5B encoder converts ...
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Code Group Symbol Final Version: DM9000B-13-DS-F02 ...
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Receiver The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data. The receive section contains the following functional blocks: - Signal Detect - Digital Adaptive Equalization - MLT-3 to ...
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Code Group Alignment The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into 5B code group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on a ...
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Power Reduced Mode The Signal detect circuit is always turned to monitor whether there is any signal on the media (cable disconnected). The DM9000B automatically turns off the power and enters the Power Reduced mode, whether its operation mode ...
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... Min. Typ 2 2 1.8 1.9 2.0 4.4 5 │19│ │20│ │44│ │50│ DM9000B Max. Unit Conditions 3.6 V 5.5 V 3.6 V +150 ℃ +70 ℃ +260 DM9000BEP ℃ Typ. Max. Unit 3.300 3.465 V 130 --- mA 170 --- mA 160 --- mA 60 --- mA 60 --- mA 20 --- mA 6 --- mA Max. Unit Conditions 0 VIN = 0. VIN = 3 ...
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AC Electrical Characteristics & Timing Waveforms 10.3.1 TP Interface Symbol Parameter t 100TX+/- Differential Rise/Fall Time TR/F t 100TX+/- Differential Rise/Fall Time TM Mismatch t 100TX+/- Differential Output Duty Cycle TDC Distortion T 100TX+/- Differential Output Peak-to-Peak t/T Jitter ...
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Processor I/O Read Timing CS#,CMD IOR# SD Symbol T CS#,CMD valid to IOR# valid 1 T IOR# width 2 T System Data(SD) Delay time 3 T IOR# invalid to System Data(SD) invalid 4 T IOR# invalid to CS#,CMD invalid ...
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Processor I/O Write Timing CS#,CMD IOW# SD Symbol T CS#,CMD valid to IOW# valid 1 T IOW# Width 2 T System Data(SD) Setup Time 3 T System Data(SD) Hold Time 4 T IOW# Invalid to CS#,CMD Invalid 5 T ...
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EEPROM Interface Timing EECS EECK EEDIO Symbol T EECK Frequency 1 T EECK Frequency, if PHYceiver is power-down 1 T2 EECS Setup Time T EECS Hold Time 3 T EEDIO Setup Time when output 4 T5 EEDIO Hold Time ...
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Application Notes 11.1 Network Interface Signal Routing Place the transformer as close as possible to the RJ-45 connector. Place all the 50Ω resistors as close as possible to the DM9000B RXI± and TXO± pins. Traces routed from RXI± and ...
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Non Auto MDIX Transformer Application ) Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Figure 11-2 Non Auto MDIX Transformer Application DM9000B 50 ...
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Power Decoupling Capacitors Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to the power pads of the DM9000B (The best placed distance is < 3mm from pin). The recommended decoupling ...
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Ground Plane Layout Davicom Semiconductor recommends a single ground plane approach to minimize EMI. Ground plane partitioning can cause increased EMI emissions that could make the network interface card not comply with specific FCC Final Version: DM9000B-13-DS-F02 June 4, ...
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Power Plane Partitioning The power planes should be approximately illustrated in Figure 11-5. Final Version: DM9000B-13-DS-F02 June 4, 2009 Ethernet Controller with General Processor Interface Figure 11-5 Power Plane Partitioning DM9000B 53 ...
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Magnetic Selection Guide Refer to Table 2 for transformer requirements. Transformers, meeting these requirements, are available from a variety of magnetic manufacturers. Designers should test and qualify all magnetic before using them in an application. The transformers listed in ...
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Package Information LQFP 48L (F.P. 2mm) Outline Dimensions Symbol Dimensions in inches Min. Nom. Max 0.063 A1 0.002 - 0.006 A2 0.053 0.055 0.057 b 0.007 0.009 0.011 b1 0.007 0.008 0.009 C 0.004 - 0.008 ...
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... Ordering Information Part Number Pin Count DM9000BEP 48 Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description ...