L-USS820FD-DB AGERE [Agere Systems], L-USS820FD-DB Datasheet - Page 9

• Manufacturer Part Number: L-USS820FD-DB
• Description: USB Device Controller
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Rev. 1
August 2004
Agere Systems Inc.
Register Timing Characteristics
All register timing specifications assume a 100 pF load on the D[7:0] package pins and a 70 pF load on all other
package pins.
Table 4. Timing Parameters
Table 5. Register Access Timing—Special Function Register (SFR) Read
IOCSN
tRDRECRXD
RDN
Symbol
tRDDV1,
tRDAHD
tRDREC
tRDASU
Symbol
tRDDV2
tRDPW
tRDDZ
D
A
t
t
RST
CLK
HIGH IMPEDANCE
Internal Clock Period.
RESET Assert Time.
Read Address Setup Time. Starts before the trailing edge of
RDN or IOCSN, whichever is first.
Read Address Hold. Starts after the trailing edge of RDN or
IOCSN, whichever is first:
Read Data Valid. From the leading edge of RDN or IOCSN or
from address valid, whichever is last, to data valid:
Read Data to Z State. Starts after the trailing edge of RDN or
IOCSN, whichever is first.
Recovery Time Between Reads. From the trailing edge of RDN
or IOCSN, whichever is first, to the next leading edge of RDN or
IOCSN, whichever is last.
Recovery Time Between Consecutive RXDAT Reads. From the
trailing edge of RDN or IOCSN, whichever is first, to the next
trailing edge of RDN or IOCSN, whichever is first.
Minimum Pulse Width. From the leading edge of RDN or
IOCSN, whichever is last, to the trailing edge of RDN or IOCSN,
whichever is first.
Operational
Suspended
Operational
Suspended
tRDDV1
Figure 5. Register Access Timing—SFR Read
tRDPW
tRDASU
tRDDV2
VALID
Parameter
Parameter
VALID
tRDDZ
tRDREC
tRDAHD
tRDRECRXD
USB Device Controller
Min
500
Min
−10
—
60
−1
23
86
23
—
—
2
VALID
Max
83.3
Max
—
74
33
32
—
—
—
—
—
—
USS-820FD
VALID
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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