L-USS820FD-DB AGERE [Agere Systems], L-USS820FD-DB Datasheet - Page 11

• Manufacturer Part Number: L-USS820FD-DB
• Description: USB Device Controller
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Rev. 1
August 2004
Agere Systems Inc.
Register Interface
The USS-820FD is controlled through an asynchronous, read/write register interface. Registers are addressed via
the A[4:0] pins, and control is provided through the RDN, WRN, and IOCSN pins. Reserved bits of registers must
always be written with 0. Writing 1 to these bits may produce undefined results. These bits return undefined values
when read.
A register read is accomplished by placing the register address on the A bus and asserting the IOCSN and RDN
pins. After read data valid (tRDDV), the register data will appear on the D bus. A register write is accomplished by
placing the register address on the A bus and the data to be written on the D bus, and asserting the IOCSN and
WRN pins.
Tables 7 and 8 show alphabetical and numerical listings of all the available special function registers (SFR) for the
USS-820FD. For reference purposes, an alphabetized list of SFR bit names is included in Appendix A. Tables 12—
39 provide details for each of the registers. Some of these registers are replicated for each endpoint. The individ-
ual, endpoint-specific register is selected by the EPINDEX register.
Table 7. Special Function Registers (By Name)
* Contains shared bits. See Special Firmware Action for Shared Register Bits section.
† Indexed by EPINDEX.
SCRATCH
EPINDEX
RXCNTH
RXSTAT*
TXCNTH
Register
EPCON*
RXCNTL
TXCNTL
TXSTAT
RXCON
TXCON
FADDR
RXDAT
RXFLG
DSAV1
TXDAT
TXFLG
SOFH*
SOFL*
MCSR
SBIE1
LOCK
PEND
DSAV
SBI1*
SSR*
SBIE
REV
SBI*
SCR
Data Set Available
Data Set Available 1
Endpoint Control Register
Endpoint Index Register
Function Address Register
Suspend Power-Off Locking Register
Miscellaneous Control/Status Register
Pend Hardware Status Update Register
Hardware Revision Register
Receive FIFO Byte-Count High Register
Receive FIFO Byte-Count Low Register
Receive FIFO Control Register
Receive FIFO Data Register
Receive FIFO Flag Register
Endpoint Receive Status Register
Serial Bus Interrupt Register
Serial Bus Interrupt Register 1
Serial Bus Interrupt Enable Register
Serial Bus Interrupt Enable Register 1
System Control Register
Scratch Firmware Information Register
Start of Frame High Register
Start of Frame Low Register
System Status Register
Transmit FIFO Byte-Count High Register
Transmit FIFO Byte-Count Low Register
USB Transmit FIFO Control Register
Transmit FIFO Data Register
Transmit FIFO Flag Register
Endpoint Transmit Status Register
Description
Address
0DH
0CH
0BH
07H
06H
08H
05H
09H
02H
01H
03H
00H
04H
1DH
0AH
1CH
1EH
10H
19H
1AH
18H
14H
15H
16H
17H
1BH
0FH
0EH
12H
11H
†
†
†
†
†
†
†
†
†
†
†
†
†
Table
38
39
19
18
22
34
37
35
33
28
28
29
27
30
21
14
15
12
13
31
36
16
17
32
24
24
25
23
26
20
USB Device Controller
Page
39
39
20
19
25
37
38
37
36
30
30
30
29
32
23
16
17
15
15
35
37
18
19
36
25
25
26
25
27
21
USS-820FD
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