L-USS820FD-DB AGERE [Agere Systems], L-USS820FD-DB Datasheet
L-USS820FD-DB
Related parts for L-USS820FD-DB
L-USS820FD-DB Summary of contents
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... TFSBGAC. (Lead-free package also avail- able. (See Ordering Information on page 51.) Evaluation kit available. Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact your Agere Systems Account Manager to obtain the latest advisory on this product. Data Sheet, Rev. 1 ...
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... FIFO Programmability .............................................................................................................................................4 FIFO Access ........................................................................................................................................................... 4 Transmit FIFO ...................................................................................................................................................... 5 Receive FIFO ....................................................................................................................................................... 6 Pin Information .........................................................................................................................................................7 Register Timing Characteristics.................................................................................................................................9 Register Interface ....................................................................................................................................................11 Special Firmware Action for Shared Register Bits ................................................................................................13 Register Reads with Side Effects..........................................................................................................................14 Register Descriptions ............................................................................................................................................15 Interrupts .................................................................................................................................................................40 Firmware Responsibilities for USB SETUP Commands..........................................................................................41 Other Firmware Responsibilities..............................................................................................................................42 Frame Timer Behavior.............................................................................................................................................42 Suspend and Resume Behavior ...
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... The USS-820FD can be clocked either by connecting a 12 MHz crystal to the XTAL1 and XTAL2 pins using a 12 MHz external oscillator. The internal 12 MHz clock period, which is a function of either of these clock sources, is referred to as the device clock period (t throughout this data sheet ...
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... ARM and ATM bits of RXCON and TXCON, respec- tively. A successful USB transaction causes FIFO access to be advanced to the next data set. A failed USB transaction (e.g., for receive operations, FIFO overrun, data time-out, CRC error, bit stuff error; for ...
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... The CPU writes to the FIFO location that is specified by the write pointer. After a write, the write pointer automati- cally increments by 1. The read marker points to the first byte of data written to a data set, and the read pointer points to the next FIFO location to be read by the USB interface. After a read, the read pointer automatically incre- ments by 1 ...
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... After a write, the write pointer automatically increments by 1. The write marker points to the first byte of data written to a data set, and the read pointer points to the next FIFO location to be read by the CPU. After a read, the read pointer automatically increments by 1. ...
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... Data Sheet, Rev. 1 August 2004 Pin Information A1 BALL PAD CORNER Note: Refer to the outline drawing on page 51 for a bottom view. Figure 4. USS-820FD Ball Diagram (48-Ball TFSBGAC) Top View Table 2. USS-820FD (48-Ball TFSBGAC) Ball Coordination Table Ball Pin Name Number Number A1 DPPU A2 NC ...
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... A8 RDN A7, B6, A6, B5, D[7:0] I/O A5, A4, B3 Active-low signals within this document are indicated following the symbol names. † Pins marked as NC must have no external connections, except where noted. 8 Name/Description 3.3 V Power Supply for Analog PLL. I Crystal/Clock Input. If the internal oscillator is used, this is the crystal input. ...
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... Data Sheet, Rev. 1 August 2004 Register Timing Characteristics All register timing specifications assume a 100 pF load on the D[7:0] package pins and load on all other package pins. Table 4. Timing Parameters Symbol t Internal Clock Period. CLK t RESET Assert Time. RST Table 5. Register Access Timing—Special Function Register (SFR) Read ...
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... Write Data Hold. From the trailing edge of WRN or IOCSN, whichever is first, to data not valid. tWRREC Recovery Time Between Write Attempts. From the trailing edge of WRN or IOCSN, whichever is first, to the next leading edge of WRN or IOCSN, whichever is last. tWRRECC Recovery Time Between Write Completes. From the trailing edge of WRN or IOCSN, whichever is first, to the next trailing edge of WRN or IOCSN, whichever is first ...
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... A register read is accomplished by placing the register address on the A bus and asserting the IOCSN and RDN pins. After read data valid (tRDDV), the register data will appear on the D bus. A register write is accomplished by placing the register address on the A bus and the data to be written on the D bus, and asserting the IOCSN and WRN pins. ...
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... Scratch Firmware Information Register 1CH MCSR Miscellaneous Control/Status Register 1DH DSAV Data Set Available 1EH DSAV1 Data Set Available 1 * Indexed by EPINDEX. † Contains shared bits. See Special Firmware Action for Shared Register Bits section. 12 Description Data Sheet, Rev. 1 August 2004 Table Page ...
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... FIFO before resetting the PEND bit the receive done indication of the second data set was in fact saved in the pended SBI/ SBI1 register, then the standard copy of the SBI/SBI1 bit will be set when firmware resets the PEND bit to 0. USS-820FD Update Behavior ...
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... USS-820FD USB Device Controller Register Interface (continued) In this case, the SBI/SBI1 bit will be set even though there is no corresponding data set present in the receive FIFO. Therefore, firmware must be prepared to service a receive done interrupt where no data sets are present in the indicated FIFO. ...
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... FTXIE4 Function Transmit Interrupt Enable 4. Enables transmit done interrupt for endpoint 4 (FTXD4). * For all bits indicates that the interrupt is enabled and causes an interrupt to be signaled to the microcontroller indicates that the asso- ciated interrupt source is disabled and cannot cause an interrupt. However, the interrupt bit’s value is still reflected in the SBI/SBI1 register. All of these bits can be read/written by firmware ...
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... If TXNAKE = 1, this also may indicate that a NAK was sent to the host in response packet that was received when TXFIF = 00. This condition also sets TXVOID. This SBI/SBI1 setting will persist until firmware clears TXVOID (or clears TXNAKE) ...
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... If TXNAKE = 1, this also may indicate that a NAK was sent to the host in response packet that was received when TXFIF = 00. This condition also sets TXVOID. This SBI/SBI1 setting will persist until firmware clears TXVOID (or clears TXNAKE) ...
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... Time Stamp Received from Host. TS[10:8] are the upper 3 bits of the 11-bit frame number issued with an SOF token. This time stamp is valid only if the SOFACK bit is set shared bit PEND must be set when writing this bit. See Special Firmware Action for Shared Register Bits section. 18 Bit 4 ...
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... See the Receive FIFO section for more details. * The EPINDEX register identifies the endpoint pair and selects the associated transmit and receive FIFO pair. The value in this register plus SFR addresses select the associated band of endpoint-indexed SFRs (TXDAT, TXCON, TXFLG, TXCNTH/L, RXDAT, RXCON, RXFLG, RXCNTH/L, EPCON, TXSTAT, and RXSTAT) ...
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... IN token. This bit is hardware read only. Note: Endpoint 0 is enabled for transmission upon reset shared bit PEND must be set when writing this bit. See Special Firmware Action for Shared Register Bits section. 20 Bit 4 ...
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... SOF, setting TXFLUSH. * For normal operation, this bit should not be modified by the user except as required by the implementation of USB standard commands, such as SET_CONFIGURATION, SET_INTERFACE, and CLEAR_FEATURE [stall]. The SIE handles all sequence bit tracking required by normal USB traffic, as documented in the USB specification, Section 8.6. † ...
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... For isochronous transactions, TXACK is not updated until the next SOF. This bit is not updated at SOF if TXFLUSH is performed. * For normal operation, this bit should not be modified by the user except as required by the implementation of USB standard commands, such as SET_CONFIGURATION, SET_INTERFACE, and CLEAR_FEATURE [stall]. The SIE handles all sequence bit tracking required by normal USB traffic, as documented in the USB specification, Section 8.6. † ...
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... SET_CONFIGURATION, SET_INTERFACE, and CLEAR_FEATURE [stall]. The SIE handles all sequence bit tracking required by normal USB traffic, as documented in the USB specification, Section 8.6. † shared bit PEND must be set when writing this bit. See Special Firmware Action for Shared Register Bits section. Agere Systems Inc. ...
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... OUT token. Receive void is closely associated with the NACK/STALL handshake returned by the function after a valid OUT token. This void condition occurs when the endpoint input is disabled (RXIE = 0) or stalled (RXSTL = 1), the FIFO contains a setup packet (RXSETUP = 1), the FIFO has no available data sets (RXFIF = 11, or RXFIF = 01/10 and RXSPM = 1), or there is an existing FIFO error (RXURF = 1 or RXOVF = 1) ...
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... Reserved. Write 0s to these bits. Reads always return 0s. 9:0 BC[9:0] Transmit Byte Count (Write, Conditional Read). 10-bit, ring buffer. These bits store transmit byte count (TXCNT). Note: To send a status stage after a control write, no data control command or a null packet, write TXCNT. Agere Systems Inc. Bit 4 Bit 3 A5 ...
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... This bit is effective only when the ADVRM, ATM, and TXCLR bits are all clear. * Assumes MCSR.FEAT = 1. If MCSR.FEAT = 0, these FFSZ settings indicate 64 bytes. † ATM mode is recommended for normal operation. ADVRM and REVRP, which control the read marker and read pointer when ATM = 0, are used for test purposes. 26 ...
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... The TXFIF bits are set in sequence after each write to TXCNT to reflect the addition of a data set. Likewise, the TXFIF1 and TFIF0 are cleared in sequence after each advance of the read marker to indicate that the set is effectively discarded. The bit is cleared whether the read marker is advanced by firmware (setting ADVRM) or automatically by hardware (ATM = 1) ...
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... TXFIF[1:0] Transmit FIFO Index Flags (Read Only) (continued). If MCSR.FEAT = 1: TXFIF bits are not visible to the host until the first SOF is written, which occurs after the data set. Prior to that SOF, the device will return a zero-length data set in response (unless there is another, older data set present from the prior frame). This ensures that a given data set may only be sent during the subsequent frame, as required by the USB specification ...
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... TXOVF Transmit FIFO Overrun Flag (Read, Clear Only). This bit is set when an additional byte is written to a full FIFO, or TXCNT is written while TXFIF[1:0] = 11. This bit must be cleared by firmware through TXCLR. When this bit is set, the FIFO unknown state; thus recommended that the FIFO is reset in the error management routine using the TXCLR bit in TXCON. When the transmit FIFO overruns, the write pointer does not advance ...
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... Table 28. Receive FIFO Byte-Count High and Low Registers (RXCNTH, RXCNTL)—Address: RXCNTH = 07H, RXCNTL = 06H; Default: RXCNTH = 0000 0000B, RXCNTL = 0000 0000B High and low registers are in a two-register ring buffer that is used to store the byte count for the data packets received in the receive FIFO specified by EPINDEX. These registers are endpoint indexed. ...
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... REVWP is used when a data packet is bad. When the function interface receives the data packet again, the write starts at the origin of the previous (bad) data set. * ARM mode is recommended for normal operation. ADVWM and REVWP, which control the write marker and write pointer when ARM = 0, are used for test purposes. ...
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... USB Device Controller USB Device Controller Register Interface (continued) Table 30. Receive FIFO Flag Register (RXFLG)—Address: 09H; Default: 0000 1000B These flags indicate the status of the data packets in the receive FIFO specified by EPINDEX. This register is endpoint indexed. Bit 7 Bit 6 Bit 5 RXFIF1 ...
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... SOF). Firmware must not be late on consecutive frames— this will cause a loss of frame/data synchronization with the host—data sets may be visible to firmware during the wrong frame. Firmware must always set RXFFRC at the end of a data set read, even if RXFLUSH = 1. RXFLUSH is reset the setting of RXFFRC RXEMP Receive FIFO Empty Flag (Read Only) ...
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... RXOVF Receive FIFO Overrun Flag (Read, Clear Only). This bit is set when the SIE writes an additional byte to a full receive FIFO or writes a byte count to RXCNT with RXFIF[1:0] = 11. This bit must be cleared by firmware through RXCLR, although it can be cleared by hardware if a SETUP packet is received after an RXOVF error has already occurred. ...
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... If MCSR.FEAT = 1, SSR.SUPPO = 0 and MCSR.SUSPLOE = 0: This bit may also be set to 1 while the device is suspended. The effect of this write is to wake up the device remote wake-up had been performed, with the following excep- tions: 1) Resume signaling is not transmitted to the host, 2) The feature is enabled regard- less of the SCR ...
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... IE_RESET set), an interrupt is generated to the controller. Firmware clears this bit shared bit PEND must be set when writing this bit. See Special Firmware Action for Shared Register Bits section. Table 33. Hardware Revision Register (REV)—Address: 18H; Default: 0001 0011B This register contains the hardware revision number, which will be incremented for each version of the hardware ...
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... This register contains the control and status which enables the USS-820FD locking mechanism. This feature protects the internal register set from being corrupted during and immediately after a suspend where the external controller is powered off. The feature is enabled by the SUSPLOE bit, and its proper usage is documented in the Special Action Required by USS-820/USS-825 After Suspend Application Note (AP97-058CMPR-04). ...
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... Updated by hardware on each wake-up from a suspended state. This bit is set the wake-up was caused by a remote wake-up event (RWUPN pin asserted). Otherwise reset to 0 (on a global resume or USB reset). If RWUPN is asserted simultaneously with a global wake-up, the bit is reset to 0 (global wake-up wins). When set, this bit indicates that resume signaling will be transmitted upstream ...
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... For receive FIFOs, this register indicates that one or more data sets 5 RXAV2 are available to be read. For transmit FIFOs, this register indicates that one or more data 4 TXAV2 sets are available to be written. Bits always read 0 for endpoints which are not enabled ...
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... Each status bit has a corresponding enable bit that allows the event to cause an interrupt. Interrupts can be masked globally by the T_IRQ bit of the SCR register. The active level and signaling mode (level vs. pulse) of the IRQN output pin can be controlled by the IRQPOL and IRQLVL bits of the SCR register. All interrupts have equal priority— ...
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... FIFO while hardware is writing a new setup packet. Firmware must reset the EDOVW bit, read the SETUP command from the FIFO, and then check the STOVW and EDOVW bits. If either is set, the SETUP that was just read out is old and should be discarded. Firmware must then proceed with reading the new SETUP command. ...
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... USB host frame timer, and to synthesize lost SOF packets, as required by the USB specification. The frame timer requires three valid SOF packets from the host in order to lock to the host frame timer. This locked status is indicated by the FTLOCK status bit in SOFH. In order to achieve this ...
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... The following sections describe each of these steps in more detail. Hardware Suspend Detect The USS-820FD detects a USB suspend condition state persists on the bus for at least 3 ms. When this suspend condition is detected, hardware sets the SSR.SUSPEND register status bit and, if IE_SUSP = 1, causes an interrupt. ...
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... Note: Board signals which are connected to powered- off components will most likely be naturally pulled to logic 0 by the powered-off component. A[4:0], IOCSN, RDN, WRN: Input-only pins. Their value will be determined by external logic, and must be a logic avoid current draw in the USS- 820FD. August 2004 Agere Systems Inc. ...
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... D[7:0], SOFN*: Bidirectional pins, forced to input mode while suspended (assuming SSR.SUSPPO = 1). Their value will be determined by external logic, and must be a logic avoid current draw in the USS-820FD. IRQN, USBR, DSA: 3-statable outputs, forced to 3-state during suspend (assuming SSR.SUSPPO = 1, MCSR.BDFEAT = 0). Their value will be determined by external logic, and is a don’ ...
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... In applications where the external controller is powered off during suspend (firmware has set SSR.SUSPPO), the SOFN pin must be connected to an external pull-down even if the pin is not functionally required. The pin is actu- ally bidirectional, where the input mode is only used in chip test modes. The pull-down is required to avoid exces- sive power consumption by the input stage when the device is suspended ...
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... Leakage Current (D[7:0], SOFN) Leakage Current (USBR, DSA, DPPU) Leakage Current (XTAL1, A[4:0], RWUPN, IRQN, RESET, IOCSN, RDN, WRN) Note: These parameters may vary slightly when operating at ambient temperatures below 0 °C. Agere Systems Inc ° ° 3.3 V ± 0.165 Symbol Test Conditions ...
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... USB. All current values assume load on the package pins. The limit for suspended devices can only be met if careful measures are taken to control the interface to the USS- 820FD, as documented in the Suspend and Resume Behavior section. ...
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... The physical connection of the USS-820FD to the USB bus requires only minimal components to provide proper USB electrical terminations. Both DPLS and DMNS require 24 Ω ± 1% series resis- tors for USB impedance matching. Additionally, a 1.5 kΩ pull-up resistor is required on DPLS for full- speed/low-speed differentiation. ...
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... Oscillator Connection Requirements The USS-820FD requires an internal 48 MHz clock that it creates from an internal 12 MHz clock via a 4X PLL. Two methods of clock generation may be used to create this internal 12 MHz clock. Figure 10 shows the internal oscil- lator mode which requires only an external 12 MHz crystal and bias capacitors. The values of the capacitors should be chosen as indicated by the crystal manufacturer in order to cause the crystal to operate in a parallel resonant condition ...
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... Dimensions are in millimeters. A 0.36 ± 0.08 0.21 ± 0.08 Ordering Information Device Code USS820FD L-USS820FD-DB 48-Ball TFSBGAC (lead-free effort to better serve its customers and the environment, Agere is converting to lead-free material set on this product. Agere Systems Inc. Note: 1. GLOBAL PLANE IS BEST FIT PLANE AS DETERMINED 2. THIS PACKAGE CONFIGURATION HAS SOLDER MASK 3 ...
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... USS-820FD USB Device Controller USB Device Controller Appendix A. Special Function Register Bit Names Table 48. Alphabetical Listing of Special Function Register Bit Names Bit Name Register Table A[6:0] FADDR ADVRM TXCON ADVWM RXCON ARM RXCON ASOF SOFH ATM TXCON BC[7:0] RXCNTL BC[7:0] TXCNTL BC[9:8] RXCNTH BC[9:8] TXCNTH BDFEAT ...
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... Data Sheet, Rev. 1 August 2004 Appendix B. USS-820FD Register Map Table 49. USS-820FD Register Map Register TXDAT TXCNTL TXCNTH TXCON TXCLR TXFFSZ[1:0] TXFLG TXFIF[1:0] RXDAT RXCNTL RXCNTH RXCON RXCLR RXFFSZ [1:0] RXFLG RXFIF[1:0] EPINDEX EPCON RXSTL TXSTL TXSTAT TXSEQ TXDSAM RXSTAT RXSEQ RXSETUP SOFL ...
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... Transmit isochronous behavior changed to discard old data packets at the end of the intended frame if not read out by a host IN (only enabled if FEAT = 1). Data sets are not visible to the host until the first SOF following the data set write. At the start of a series of transfers, TXFIF will equal 00, which could allow firmware to write two data sets during that same frame ...
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... USB Device Controller Appendix D. Changes from USS-820 Revision All (4) USS-820C/USS-820TC advisory items are corrected. 2. Value of REV register is changed from 11h to 13h. Appendix E. Changes from USS-820 Revision Device package was changed from a 44-pin MQFP or a 48-pin TQFP to a 48-ball TFSBGAC. ...
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... Tel. (44) 1344 296 400 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems and the Agere logo are trademarks of Agere Systems Inc. ...