L-USS820FD-DB AGERE [Agere Systems], L-USS820FD-DB Datasheet - Page 3

• Manufacturer Part Number: L-USS820FD-DB
• Description: USB Device Controller
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Rev. 1
August 2004
Description
USS-820FD is a USB device controller that provides a
programmable bridge between the USB and a local
microprocessor bus. It is available in a 48-ball
TFSBGAC package. The USS-820FD allows PC
peripherals to upgrade to USB connectivity without
major redesign effort. It is programmable through a
simple read/write register interface that is compatible
with industry-standard USB microcontrollers.
USS-820FD is designed in 100% compliance with the
USB industry standard, allowing device-side USB prod-
ucts to be reliably installed using low-cost, off-the-shelf
cables and connectors.
The integrated USB transceiver supports 12 Mbits/s
full-speed operation. FIFO options support all four
transfer types: control, interrupt, bulk, and isochronous,
as described in Universal Serial Bus Specification
Revision 1.1, with a wide range of packet sizes. Its
double sets of FIFO enable the dual-packet mode
feature. The dual-packet mode feature reduces latency
by allowing simultaneous transfers on the host and
microprocessor sides of a given unidirectional
endpoint.
The USS-820FD supports a maximum of eight bidirec-
tional endpoints with 16 FIFOs (eight for transmit and
eight for receive) associated with them. The FIFOs are
on-chip, and sizes are programmable up to a total of
1120 logical bytes. When the dual-packet mode feature
is enabled, the device uses a maximum of 2240 bytes
of physical storage. This additional physical FIFO stor-
age is managed by the device hardware and is trans-
parent to the user.
The FIFO sizes supported are 8 bytes, 16 bytes,
Agere Systems Inc.
DMNS
DPLS
V
V
DD
SS
PLL
XCVR
USB
OSCILLATOR
DIGITAL
PLL
Figure 1. Block Diagram
SIE
USS-820FD
32 bytes, and 64 bytes for nonisochronous pipes, and
64 bytes, 256 bytes, 512 bytes, and 1024 bytes for iso-
chronous pipes. The FIFO size of a given endpoint
defines the upper limit to maximum packet size that the
hardware can support for that endpoint. This flexibility
covers a wide range of data rates, data types, and
combinations of applications.
The USS-820FD can be clocked either by connecting a
12 MHz crystal to the XTAL1 and XTAL2 pins, or by
using a 12 MHz external oscillator. The internal 12 MHz
clock period, which is a function of either of these clock
sources, is referred to as the device clock period (t
throughout this data sheet.
Serial Interface Engine
The SIE is the USB protocol interpreter. It serves as a
communicator between the USS-820FD and the host
through the USB lines.
The SIE functions include the following:
PROTOCOL
Package protocol sequencing.
SOP (start of packet), EOP (end of packet),
RESUME, and RESET signal detection and genera-
tion.
NRZI data encoding/decoding and bit stuffing.
CRC generation and checking for token and data.
Serial-to-parallel and parallel-to-serial data conver-
sion.
LAYER
CONTROL
FIFOs
FIFO
USB Device Controller
MICROPROCESSOR
EXTERNAL
USS-820FD
BUS
CLK
5-8121
)
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