L-USS820FD-DB AGERE [Agere Systems], L-USS820FD-DB Datasheet - Page 24

• Manufacturer Part Number: L-USS820FD-DB
• Description: USB Device Controller
• Manufacturer: AGERE [Agere Systems]

USS-820FD
USB Device Controller
USB Device Controller
Register Interface
Table 21. Endpoint Receive Status Register (RXSTAT)—Address: 0DH; Default: 0000 0000B (continued)
24
Bit
2
1
0
RXVOID
Symbol
RXERR
RXACK
Receive Void (Read Only). Indicates a void condition has occurred in response to a
valid OUT token. Receive void is closely associated with the NACK/STALL handshake
returned by the function after a valid OUT token. This void condition occurs when the
endpoint input is disabled (RXIE = 0) or stalled (RXSTL = 1), the FIFO contains a setup
packet (RXSETUP = 1), the FIFO has no available data sets (RXFIF = 11, or RXFIF =
01/10 and RXSPM = 1), or there is an existing FIFO error (RXURF = 1 or RXOVF = 1).
This bit is set and cleared by hardware. For nonisochronous transactions, this bit is
updated by hardware at the end of the transaction in response to a valid OUT token. For
isochronous transactions, it is not updated until the next SOF.
Receive Error (Read Only). Set when an error condition has occurred with the recep-
tion of a SETUP or OUT transaction. Complete or partial data has been written into the
receive FIFO. No handshake is returned. The error can be one of the following:
1. Data failed CRC check.
2. Bit stuffing error.
3. A receive FIFO goes into overrun or underrun condition while receiving.
This bit is updated by hardware at the end of a valid SETUP or OUT token transaction
(nonisochronous) or at the next SOF on each valid OUT token transaction (isochro-
nous).
These conditions also cause the corresponding FRXDx bit of SBI or SBI1 to be set.
RXERR is updated with the RXACK bit at the end of data reception. RXERR and
RXACK are updated at the same time—one bit is set to 1, and the other is reset to 0.
Receive Acknowledge (Read Only). This bit is set when an ACK handshake is sent in
response to data being written to the receive FIFO. This read-only bit is updated by
hardware at the end of a valid SETUP or OUT token transaction (nonisochronous) or at
the next SOF on each valid OUT token transaction (isochronous).
This condition also causes the corresponding FRXDx bit of SBI or SBI1 to be set.
RXACK is updated with the RXERR bit at the end of data reception. RXERR and
RXACK are updated at the same time—one bit is set to 1, and the other is reset to 0.
(continued)
Function/Description
Data Sheet, Rev. 1
Agere Systems Inc.
August 2004