L-USS820FD-DB AGERE [Agere Systems], L-USS820FD-DB Datasheet - Page 31

• Manufacturer Part Number: L-USS820FD-DB
• Description: USB Device Controller
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Rev. 1
August 2004
Agere Systems Inc.
Register Interface
Table 29. Receive FIFO Control Register (RXCON)—Address: 08H; Default: 0000 0100B (continued)
* ARM mode is recommended for normal operation. ADVWM and REVWP, which control the write marker and write pointer when ARM = 0, are
used for test purposes.
Bit
4
3
2
1
0
RXFFRC
ADVWM
REVWP
Symbol
RXISO
ARM
FIFO Read Complete. When set, the receive FIFO is released when a data set read is
complete. Setting this bit clears the RXFIF bit (in the RXFLG register), corresponding to
the data set that was just read. Hardware clears this bit after the RXFIF bit is cleared. All
data from this data set must have been read. For isochronous endpoints, firmware must
check RXFLUSH before setting RXFFRC, and the act of setting RXFFRC clears
RXFLUSH. See RXFLUSH description for details.
Note: FIFO read complete only works if the STOVW and EDOVW bits are both cleared.
Receive Isochronous Data. When set, this indicates that the receive FIFO is
programmed to receive isochronous data and to set up the USB interface to handle an
isochronous data transfer.
Auto Receive Management.* When set, the write pointer and write marker are adjusted
automatically based on the following conditions:
This bit should always be set, except for test purposes. When this bit is set, setting
REVWP or ADVWM has no effect. Hardware neither clears nor sets this bit. This bit can be
set and cleared by firmware. This bit must always be set for isochronous endpoints
(RXISO = 1).
Advance Write Marker (Non-ARM Mode Only).* When set, the write marker is advanced
to the origin of the next data set. Advancing the write marker is used for back-to-back
receptions. Hardware clears this bit after the write marker is advanced. Setting this bit is
effective only when the REVWP, ARM, and RXCLR bits are clear.
Reverse Write Pointer (Non-ARM Mode Only).* When set, the write pointer is returned
to the origin of the last data set received, as identified by the write marker. The SIE can
then reread the last data packet and write to the receive FIFO starting from the same
origin when the host resends the same data packet. Hardware clears this bit after the write
pointer is reversed. Setting this bit is effective only when the ADVWM, ARM, and RXCLR
bits are clear.
REVWP is used when a data packet is bad. When the function interface receives the data
packet again, the write starts at the origin of the previous (bad) data set.
(continued)
RX Status
NACK
ACK
Write Pointer
Unchanged
Reversed
Function/Description
Write Marker
Unchanged
Advanced
USB Device Controller
USS-820FD
31