L-USS820FD-DB AGERE [Agere Systems], L-USS820FD-DB Datasheet - Page 4

• Manufacturer Part Number: L-USS820FD-DB
• Description: USB Device Controller
• Manufacturer: AGERE [Agere Systems]

USS-820FD
USB Device Controller
Description
Protocol Layer
The protocol layer manages the interface between the
SIE and FIFO control blocks. It passes all USB OUT
and SETUP packets through to the appropriate FIFO. It
is the responsibility of firmware to correctly interpret
and execute each USB SETUP command (as docu-
mented in the Firmware Responsibilities for USB
SETUP Commands section) via the register interface.
The protocol layer tracks the setup, data, and status
stages of control transfers.
FIFO Control
USS-820FD’s FIFO control manager handles the data
flow between the FIFOs and the device controller’s pro-
tocol layer. It handles flow control and error handling/
fault recovery to monitor transaction status and to relay
control events via interrupt vectors.
FIFO Programmability
Table 1 shows the programmable FIFO sizes. The size
of the FIFO determines the maximum packet size that
the hardware can support for a given endpoint. An end-
point is only allocated space in the shared FIFO stor-
age if its RXEPEN/TXEPEN bit = 1. If the endpoint is
disabled (RXEPEN/TXEPEN = 0), it is allocated
0 bytes. Register changes that affect the allocation of
the shared FIFO storage among endpoints must not be
made while there is valid data present in any of the
enabled endpoints’ FIFOs. Any such changes will ren-
der all FIFO contents undefined. Register bits that
affect the FIFO allocation are the endpoint enable bits
(the TXEPEN and RXEPEN bits of EPCON), the size
bits of an enabled endpoint (FFSZ bits of TXCON and
RXCON), the isochronous bit of an enabled endpoint
(TXISO bit of TXCON and RXISO bit of RXCON), and
the FEAT bit of the MCSR register.
If the MCSR.FEAT register bit is set to 1, additional
FIFO sizes are enabled for nonisochronous endpoints,
as shown in Table 1.
Table 1. Programmable FIFO Sizes
* Assumes MCSR.FEAT = 1. If this bit is 0 and FFSZ = 10 or 11, both
4 4
Nonisoch-
ronous
Isochro-
nous
FFSZ[1:0]
indicate a size of 64 bytes.
16 bytes 64 bytes
64 bytes 256 bytes 512 bytes 1024 bytes
00
(continued)
01
8 bytes*
10
32 bytes*
11
Each FIFO can be programmed independently via the
TXCON and RXCON registers, but the total logical size
of the enabled endpoints (TX FIFOs + RX FIFOs) must
not exceed 1120 bytes. The 1120-byte total allows a
configuration with a full-sized, 1024-byte isochronous
endpoint, a minimum-sized, 64-byte isochronous feed-
back endpoint, and the required, bidirectional, 16-byte
control endpoint. When the dual-packet mode feature
is enabled, the device uses a maximum of 2240 bytes
of physical storage. This additional physical FIFO stor-
age is managed by the device hardware and is trans-
parent to the user.
FIFO Access
The transmit and receive FIFOs are accessed by the
application through the register interface (see
Tables 23—26 for transmit FIFO registers and
Tables 27—30 for receive FIFO registers).
The transmit FIFO is written to via the TXDAT register,
and the receive FIFO is read via the RXDAT register.
The particular transmit/receive FIFO is specified by the
EPINDEX register. Each FIFO is accessed serially,
each RXDAT read increments the receive FIFO read
pointer by 1, and each TXDAT write increments the
transmit FIFO write pointer by 1.
Each FIFO consists of two data sets to provide the
capability for simultaneous read/write access. Control
of these pairs of data sets is managed by the hard-
ware, invisible to the application, although the applica-
tion must be aware of the implications. The receive
FIFO read access is advanced to the next data set by
firmware setting the RXFFRC bit of RXCON. This bit
clears itself after the advance is complete. The transmit
FIFO write access is advanced to the next data set by
firmware writing the byte count to the TXCNTH/L regis-
ters.
The USB access to the receive and transmit FIFOs is
managed by the hardware, although the control of the
nonisochronous data sets can be overridden by the
ARM and ATM bits of RXCON and TXCON, respec-
tively. A successful USB transaction causes FIFO
access to be advanced to the next data set. A failed
USB transaction (e.g., for receive operations, FIFO
overrun, data time-out, CRC error, bit stuff error; for
transmit operations, FIFO underrun, no ACK from host)
causes the FIFO read/write pointer to be reversed to
the beginning of the data set to allow transmission retry
for nonisochronous transfers.
Data Sheet, Rev. 1
Agere Systems Inc.
August 2004