HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 86

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

HardCopy Series Handbook, Volume 1
4–44
Notes to
(1)
(2)
Notes to
(1)
(2)
Table 4–48. DQS Phase Jitter Specifications for DLL-Delayed Clock (tDQS
PHASE_JITTER)
Table 4–49. DQS Phase-Shift Error Specifications for DLL-Delayed Clock
(tDQS_PSERR)
Number of DQS Delay Buffer
Number of DQS Delay Buffer
Peak-to-peak phase jitter on the phase shifted DDS clock (digital jitter is caused
by DLL tracking).
Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.
This error specification is the absolute maximum and minimum error. For
example, skew on three delay buffer stages with an HC240 device is 105 ps or
± 52.5 ps.
Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.
Table
Table
Stages (2))
Stages
4–48:
4–49:
1
2
3
4
1
2
3
4
Note (1)
Note (1)
(2)
HC210, HC220, HC230 HC240
DQS Phase Jitter
120
30
60
90
120
30
60
90
Altera Corporation
September 2008
Unit
Unit
ps
ps
ps
ps
ps
ps
ps
ps