HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 82

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

HardCopy Series Handbook, Volume 1
4–40
Notes to
(1)
(2)
(3)
(4)
t
t
f
f
f
f
% spread
t
t
t
LOCK
DLOCK
SWITCHOVER
CLKW
VCO
SS
PLL_PSERR
ARESET
ARESET_RECONFIG
Table 4–42. HardCopy II Enhanced PLL Specifications (Part 2 of 2)
Limited by I/O f
If the counter cascading feature of the PLL is used, there is no minimum output clock frequency.
Applicable when the PLL input clock has been running continuously for at least 10 µs.
Applicable when the PLL input clock has stopped toggling or has been running continuously for less than 10 µs.
Name
Table
4–42:
Time required for the PLL to lock
from the time it is enabled or the
end of device configuration
Time required for the PLL to lock
dynamically after automatic clock
switchover between two identical
clock frequencies
Frequency range where the clock
switchover performs properly
PLL closed loop bandwidth
PLL VCO operating range for
HC210, HC220, HC230 and HC240
devices
PLL VCO operating range for
HC210W devices
Spread spectrum modulation
frequency
Percent down spread for a given
clock frequency
Accuracy of PLL phase shift
Minimum pulse width on ARESET
signal.
Minimum pulse width on the areset
signal when using PLL
reconfiguration. Reset the PLL after
scan done goes high.
MAX
.
Description
500
10
0.13
Min
300
300
100
500
0.4
—
—
—
4
(3)
(4)
0.03
Typ
1.2
0.5
—
—
—
—
—
—
—
—
—
1,040
Max
16.9
± 15
500
840
500
0.6
—
—
—
1
1
Altera Corporation
September 2008
MHz
MHz
MHz
MHz
MHz
Unit
ms
ms
ps
ns
ns
ns
%