HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 140

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

HardCopy Series Handbook, Volume 1
6–12
VERILOG_FILE
VHDL_FILE
AHDL_FILE
EDIF_FILE
BDF_FILE
FAMILY
DEVICE
TOP_LEVEL_ENTITY
DEVICE_TECHNOLOGY_MIGRATION_LIST
COMPANION_REVISION
ENABLE_DRC_SETTINGS
USE_TIMEQUEST_TIMING_ANALYZER
SDC_FILE
You only need the following settings when using Classic Timing Analyzer. Using
Classic Timing Analyzer is not recommended.
REPORT_IO_PATHS_SEPARATELY
FLOW_ENABLE_TIMING_CONSTRAINT_CHECK
DO_COMBINED_ANALYSIS
IGNORE_CLOCK_SETTINGS
ENABLE_RECOVERY_REMOVAL_ANALYSIS
ENABLE_CLOCK_LATENCY
Table 6–4. Key HardCopy II Design Settings
Global Variable Name <name>
The key global variables for a HardCopy II project are listed in
Verilog file name.
VHDL file name.
Altera HDL file name.
EDIF file name.
Altera schematic file name.
Device family name, for example, Stratix II.
Prototype FPGA target device name.
Top-level design entity or module name.
HardCopy II target device name.
HardCopy II design revision name.
Turn on the Design Assistant.
Set TimeQuest as the default timing analyzer <ON>.
File of TimeQuest constraints <constraint_file.sdc>.
Creates a separate report panel for input and output min
and max timing results.
Timing constraints are checked for completeness (all clock
domains constraints and minimum and maximum
constraints are set for all I/O paths).
Timing analysis are run for fast and slow operating
conditions and for best and worst-case timing analysis,
respectively.
This must be turned off.
Verify recovery and removal times on asynchronous
control and reset signals.
Clock latency is included in timing analysis to asses
clock-insertion timing and clock skew.
Value Description <value>
Altera Corporation
September 2008
Table
6–4.