HC230 ALTERA [Altera Corporation], HC230 Datasheet - Page 41

• Manufacturer Part Number: HC230
• Description: HardCopy II Device Family
• Manufacturer: ALTERA [Altera Corporation]

Document
Revision History
Altera Corporation
September 2008
Date and Document
September 2008,
v2.4
June 2007, v2.3
December 2006
v2.2
October 2005, v2.1
Table 3–5. Document Revision History (Part 1 of 2)
Version
f
Updated chapter number and metadata.
●
●
●
●
●
Updated graphics.
Added resource information
Figure 3–1
New section on Boundary-Scan Test (BST) on HardCopy
II devices.
Minor updates for Quartus II 6.1.0 software version
Added revision history
For more information on JTAG or boundary-scan testing, refer to AN 39:
IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices.
1
Table 3–5
t
t
t
t
t
t
J P H
J P C O
J P Z X
J P X Z
J S S U
J S H
Table 3–4. HardCopy II JTAG Timing Parameters and Values (Part 2 of 2)
Symbol
changes
Like Stratix II FPGAs, HardCopy II devices support the
SignalTap® II embedded logic analyzer, which monitors design
operation over a period of time through the JTAG interface. The
SignalTap II logic analyzer is a useful feature during the FPGA
prototyping phase, but should be removed if not needed once
the design has been migrated to a HardCopy II device.
HardCopy II is a mask programmed device, and the Signal Tap
logic cannot be eliminated after the HardCopy II device is
fabricated.
shows the revision history for this chapter.
Changes Made
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to
valid output
JTAG port valid output to high
impedance
Capture register setup time
Capture register hold time
Parameter
Document Revision History
Updated for Quartus II 6.1
Min
5
4
5
Summary of Changes
software version.
Max
—
—
—
11
14
14
Preliminary
Unit
ns
ns
ns
ns
ns
ns
3–5